Abstract: The present disclosure provides EBNA1 and LMP1 dual-targeting peptides and upconversion nanoparticles conjugates comprising the same useful as therapeutic and theranostic agents capable of targeting EBNA1 and LMP1 proteins present in Epstein-Barr virus infected cells, such as cancer.

Abstract: This disclosure relates to a leadless packaged semiconductor device including a top and a bottom opposing major surfaces and sidewalls extending between the top and bottom surfaces, the leadless packaged semiconductor device further includes a lead frame structure including an array of two or more lead frame sub-structures each having a semiconductor die arranged thereon, and terminals and a track extended across the bottom surface of the semiconductor device. The track provides a region for interconnecting the semiconductor die and terminals, and the track is filled by an insulating material to isolate the lead frame sub-structures.

Abstract: A semiconductor device is provided, including a lead frame, a metal pad and the metal pad is connected to a back side of the semiconductor device via the lead frame. The semiconductor device further includes a die pad, and the die pad is attached to the lead frame via a die attach material, and an encapsulant that is disposed on the top surface of the lead frame. The encapsulant isolates the metal pad from the die pad.

Abstract: A semiconductor device is provided, including a first die, such as a GaN HEMT die, and a second die, such as a MOSFET die, with the second die positioned on the top of the first die. The second die is attached using a die attach adhesive. The semiconductor device further includes an encapsulant deposited on the top of the semiconductor device. The encapsulant is covering the first die and the second die. Metalized vias are created within the encapsulant, and the metalized vias are arranged to distribute terminals of the first die and the terminals of the second die to the top side of the semiconductor device.

Abstract: A semiconductor package including a lead frame, an Ag plated surface positioned on the lead frame, an adhesion promotion layer positioned on the top of the Ag plated surface, and mold body covering the top of the lead frame is provided. The Ag plated surface covers a significant part of an interconnection area of the lead frame surface, and the Ag plating surface does not exceed the area of the mold body.

Abstract: This disclosure relates to a leadless packaged semiconductor device including a top and a bottom opposing major surfaces and sidewalls extending between the top and bottom surfaces, the leadless packaged semiconductor device further includes a lead frame structure including an array of two or more lead frame sub-structures each having a semiconductor die arranged thereon, and terminals and a track extended across the bottom surface of the semiconductor device. The track provides a region for interconnecting the semiconductor die and terminals, and the track is filled by an insulating material to isolate the lead frame sub-structures.

Abstract: A leadless package semiconductor device has a top surface, a bottom surface opposite to the top surface, and multiple sidewalls between the top and bottom surfaces. At least one connection pad is disposed on the bottom surface. The connection pad includes a connection portion and at least one protrusion portion that extends from the connection portion and away from the bottom surface such that the protrusion portion and the connection portion surround a space on the bottom surface.

Abstract: A leadless package semiconductor device has a top surface, a bottom surface opposite to the top surface, and multiple sidewalls between the top and bottom surfaces. At least one connection pad is disposed on the bottom surface. The connection pad includes a connection portion and at least one protrusion portion that extends from the connection portion and away from the bottom surface such that the protrusion portion and the connection portion surround a space on the bottom surface.

Abstract: An electronic device includes a conductive layer, a device die, and a connecting member. The conductive layer is formed by coating a conductive material on a substrate. The device die and the connecting member are disposed on the conductive layer and spaced from each other. The device die includes a first connection point on one side that is in contact with and electrically connected to the conductive layer, and a second connection point on another side thereof. The connecting member includes a third connection point on a side thereof electrically connected to and in contact with the conductive layer, and a fourth connection point on another side thereof. The second and fourth connection points are configured to provide external connections of the electronic device.

Abstract: A method for forming reinforced interconnects or bumps on a substrate includes first forming a support structure on the substrate. A substantially filled capsule is then formed around the support structure to form an interconnect. The interconnect can reach a height of up to 300 microns.

Abstract: A method for forming multi-layer bumps on a substrate includes depositing an adhesive or a flux on the substrate, depositing a first metal powder on the adhesive, and melting or reflowing the adhesive and first metal powder to form first bumps. An adhesive or a flux and a second metal powder are then deposited on the first bumps, and melted to form second bumps on the first bumps to form multi-layer bumps. The multi-layer bumps are formed without the need for any wet chemicals.

Abstract: A method for forming multi-layer bumps on a substrate includes depositing a first metal powder on the substrate, and selectively melting or reflowing a portion of the first metal powder to form first bumps. A second metal powder is then deposited on the first bumps, and melted to form second bumps on the first bumps. A masking plate is disposed over the substrate to select the portions of the metal powders that are melted and the metal powders are melted via an irradiation beam. The multi-layer bump is formed without the need for any wet chemicals.

Abstract: An electronic device (60) including a first integrated circuit (IC) die (62) electrically connected to a first lead frame (64) and a second IC die (66) electrically connected to a second lead frame (68). The first lead frame (64) is electrically connected to the second lead frame (68) by at least one stud bump (72), which is selectively formed where an electrical connection between the first lead frame (64) and the second lead frame (68) is required. The first and second lead frames (64) and (68), the first and second IC dies (62) and (66), and the at least one stud bump (72) are encapsulated by a mold compound (74) to form a 3D package.