Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: The present disclosure, in an aspect, relates to a source driver to control a bias current, and more particularly, to a source driver, in which a bias current of a buffer is controlled depending on a distance between the source driver and a pixel in a data line and a position, regarding which a bias current is set, and the intensity of the bias current are changed in every frame so that unnecessary power consumption due to bias currents may be reduced and a block-dim phenomenon may be alleviated.

Abstract: A light emitting diode apparatus is provided. The light emitting diode apparatus includes a wavelength conversion layer, a light emitting diode layer, a light transmission layer, and a sheath layer. The wavelength conversion layer has a first refractive index. The light emitting diode layer includes a base layer arranged on the wavelength conversion layer, and a light emitting structure layer arranged on the base layer. The light transmission layer is arranged on the wavelength conversion layer, surrounds a sidewall of the light emitting diode layer and contacts the sidewall of the light emitting diode layer, and has a second refractive index. The sheath layer is arranged to cover the light emitting diode layer and the light transmission layer, and has a third refractive index less than the second refractive index.

Abstract: The present invention relates to a composition for screening various signal peptides to select specific ones that allow efficient secretion of a target protein to out of host cells. The present invention also relates to a method for selecting specific signal peptides that express a target protein in host cells and efficiently secrete the target protein to out of the host cells. The use of the composition and/or method according to the present invention enables ultrafast selection of optimal signal peptides for a target protein through barcoding sequences corresponding to the signal peptides, leading to the maximization of the production yield of the recombinant protein.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate a bit line structure disposed on the substrate, a trench adjacent to at least one side of the bit line structure, a storage contact structure disposed within the trench, and comprising a storage contact, a silicide layer, and a storage pad which are stacked sequentially. A spacer structure is disposed between the bit line structure and the storage contact structure.

Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.

Abstract: The present disclosure provides an operation apparatus operating based on the Winograd algorithm for multiplying a first matrix by a second matrix to generate a third matrix, including a plurality of second accumulated value calculation units, of which one second accumulated value calculation unit is configured to accumulate second multiplication values obtained by multiplying each of paired element values of the second matrix, a second accumulated value output unit outputting selecting and outputting one of output values of adjacent second accumulated value calculation unit and an accumulated second multiplication value as a second accumulated value, a third accumulated value output unit including a plurality of third accumulated value calculation units and generating third accumulated value, and one or more row element value calculation units, of which one row element value calculation unit is configured to accumulate first matrix element multiplication values obtained by multiplying each of the paired elem

Abstract: A method for manufacturing a high-strength steel bar can include the steps of: reheating a steel slab at a temperature ranging from 1000° C. to 1100° C., the steel slab including a certain amount of carbon (C), silicon (Si), manganese (Mn), phosphorus (P), sulfur (S), chromium (Cr), copper (Cu), nickel (Ni), molybdenum (Mo), aluminum (Al), vanadium (V), nitrogen (N), antimony (Sb), tin (Sn), and iron (Fe) and other inevitable impurities, The method can further include finish hot-rolling the reheated steel slab at a temperature of 850° C. to 1000° C., and cooling the hot-rolled steel to a martensite transformation start temperature (Ms (° C.)) through a tempcore process.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a write circuit and a memory cell. The write circuit is suitable for generating a first write current having a lower level than a melting current and a second write current having a higher level than the melting current during a set program operation. The memory cell is suitable for storing a data value corresponding to a write data signal, based on the first and second write currents.

Abstract: The proposed is directed to a shampoo assisting device that is mounted on a wash basin, a bathtub, a sink, etc. with a simple configuration to allow the user to be shampooed while lying down. The shampoo assisting device includes a main body having a locking part provided on one side and a headrest part provided on the other side to support a user's head, and a first support protruding from a lower portion of the main body so as to be closely supported by a bottom surface of a wash basin.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Abstract: A parallel audio transcoding method includes splitting audio into segments of a certain length; performing parallel transcoding by allocating the split segments to a plurality of encoders; and concatenating the segments encoded through the parallel transcoding and merging the same into a single encoded file. Performing parallel transcoding includes inserting additional regions, which overlap and neighbor each of the split segments, and sending the same to the encoders, and merging includes cutting out the additional regions from the encoded stream to create a stream corresponding to the split segments.

Abstract: A display device includes a pixel disposed in a display region. The pixel includes a light-emitting element connected between a first power source and a second power source; a first transistor connected between the first power source and the light-emitting element to control a driving current flowing in the light-emitting element in response to a voltage of a first node; and at least one switching transistor to transmit a data signal or a voltage of an initialization power source to the first node. The switching transistor includes a first channel region, a first conductive region and a second conductive region which are respectively disposed at opposite sides of the first channel region, and a first wide band-gap region disposed between the first channel region and the second conductive region.

Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.

Abstract: The present technology includes a method of operating a controller that controls a semiconductor memory device including a plurality of memory blocks. The method includes receiving a read request for data included in any one memory block among the plurality of memory blocks from a host, and controlling the semiconductor memory device to read data corresponding to the read request using a read-history table. The read-history table includes read voltages used for a plurality of read pass operations for the any one memory block, respectively.

Abstract: A memory system includes a memory device and a controller. The controller is coupled to the memory device through input/output (I/O) lines. The controller includes an interface component and a dummy power consumption component. The interface component performs a signal training operation for adjusting a timing of a clock signal, to which test data is synchronized. The dummy power consumption component performs a dummy power consumption operation while the signal training operation is performed.

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a substrate, a device isolation pattern between the first impurity region and the second impurity region, a bit-line contact on the first impurity region, a storage node contact on the second impurity region and a dielectric pattern between the bit-line contact and the storage node contact. An upper part of a sidewall of the device isolation pattern has a first slope and a lower part of the sidewall of the device isolation pattern has a second slope different from the first slope.