Abstract: A cellular modem processor can include dedicated processing engines that implement specific, complex data processing operations. The processing engines can be arranged in pipelines, with different processing engines executing different steps in a sequence of operations. Flow control or data synchronization between pipeline stages can be provided using a hybrid of firmware-based flow control and hardware-based data dependency management. Firmware instructions can define data flow by reference to a virtual address space associated with pipeline buffers. A hardware interlock controller within the pipeline can track and enforce the data dependencies for the pipeline.

Abstract: A vector cumulative sum circuit can include a set of input registers, a carry-forward data source, a set of output registers, and a network of adder circuits coupling the input registers to the output registers such that the output value in a given output register is the sum of a value provided by the carry-forward data source and the input values from all of the input registers (in logical order) up to (and including) the corresponding input register. The value in the last output register can be carried forward to enable cumulative summing of a larger number of input values. The vector cumulative sum circuit can be implemented in a programmable processor, and a vector cumulative sum instruction can be defined in the instruction set. Using the vector cumulative sum circuit and instruction, filtering operations can be accelerated.

Abstract: A cellular modem processor can include dedicated processing engines that implement specific, complex data processing operations. The processing engines can be arranged in pipelines, with different processing engines executing different steps in a sequence of operations. Flow control or data synchronization between pipeline stages can be provided using a hybrid of firmware-based flow control and hardware-based data dependency management. Firmware instructions can define data flow by reference to a virtual address space associated with pipeline buffers. A hardware interlock controller within the pipeline can track and enforce the data dependencies for the pipeline.

Abstract: A cellular modem processor can include dedicated processing engines that implement specific, complex data processing operations. The processing engines can be arranged in pipelines, with different processing engines executing different steps in a sequence of operations. Flow control or data synchronization between pipeline stages can be provided using a hybrid of firmware-based flow control and hardware-based data dependency management. Firmware instructions can define data flow by reference to a virtual address space associated with pipeline buffers. A hardware interlock controller within the pipeline can track and enforce the data dependencies for the pipeline.

Abstract: Vector sort circuits that can be used to accelerate sorting operations in a vector processor. When a new data element is received, the vector sort circuit can read multiple existing data elements from a vector-sort database in parallel, compare metrics of the existing data elements to a metric of the new data element, and output updated data elements to the vector-sort database based on the metrics. Depending on implementation, the vector-sort database can be maintained in sorted order, or the data elements can have assigned ranks indicating the sort order and the elements need not be stored in sorted order. A vector sort circuit can be incorporated into a vector sort functional unit of a microprocessor, and the instruction set of the microprocessor can include instructions that are executed by the vector sort functional unit using the vector sort circuit.

Abstract: Systems and methods for signal analysis are described. The method can include digitizing a signal modulated by a pseudo noise (PN) sequence, dividing the digitized signal into a plurality of sample blocks, and estimating a PN phase embedded in a sample block of the plurality of sample blocks using an iterative message passing algorithm (iMPA) executed on a redundant graphical model.

Abstract: Systems and methods for signal analysis are described. The method can include digitizing a signal modulated by a pseudo noise (PN) sequence, dividing the digitized signal into a plurality of sample blocks, and estimating a PN phase embedded in a sample block of the plurality of sample blocks using an iterative message passing algorithm (iMPA) executed on a redundant graphical model.

Abstract: This invention discloses an electrothermal ironing board, comprising a holding plate, a sponge plastics, heat-resistant insulating cloths, an electric film with metal electrodes and a cloth cover, all of which are uniform thin layers, the heating element being the electric film, disposed in order from bottom to top being the holding plate, the plastic foam, the lower heat-resistant insulating cloth, the electric film with the metal electrodes, the upper heat-resistant insulating cloth and the cloth cover; and the circuit of the ironing board comprising the electric film, the metal electrodes and a thermal switch.