Abstract: In a prefetch-type FCRAM having an improved data write control circuit and a method of masking data using the prefetch-type FCRAM, the prefetch-type FCRAM includes a command decoder, a row decoder, a column decoder, a data input buffer, a data output buffer, and a valid write window buffer. The command decoder outputs control commands including first and second write commands in response to predetermined external input signals. The row decoder decodes a row address signal input into the address pins and activates a wordline of the memory cell array corresponding to the decoded row address signal. The column decoder decodes a column address signal input into the address pins and activates a column select line of the memory cell array corresponding to the decoded column address signal. The data input buffer receives input data from the plurality of data pins and then outputs the input data in synchronization with a predetermined clock signal.

Abstract: Integrated circuit memory devices include a memory cell array that is configured to write N data bits in parallel and a write data path that is configured to serially receive 2N data bits from an external terminal. The write data path includes 2N write data buffers that are configured to store the 2N data bits, 2N switches, and N data lines that are configured to connect at least N of the 2N switches to the memory cell array to write therein N data bits in parallel. A reduced number of local data lines and/or global data lines may be provided.

Abstract: The present invention provides a dual data rate (DDR) integrated circuit memory device that is configured to support an N to 2N prefetch-to-burst length mode of operation. The DDR integrated circuit memory device is further configured to support a sequential address increase scheme and an interleave address increase scheme.

Abstract: The present invention provides a dual data rate (DDR) integrated circuit memory device that is configured to support an N to 2N prefetch-to-burst length mode of operation. The DDR integrated circuit memory device is further configured to support a sequential address increase scheme and an interleave address increase scheme.

Abstract: A circuit for receiving data to be written in a synchronous semiconductor memory device, comprising: a first set of latches for receiving an n-bit data upon transition of an internal strobe signal; a counter for counting the number of transitions of the internal strobe signal and for outputting an indicating signal upon counting the end of a string of internal strobe signals; a second set of latches for receiving the outputs of the first set of latches, the second set of latches being clocked by the indicating signal; and a third set of latches for receiving the outputs of the second set of latches, the third set of latches being clocked by a clock signal derived from a system clock.

Abstract: A semiconductor memory device having an architecture that allows a user to change a page length of the semiconductor device. Circuits and methods for changing a page length of a semiconductor device enable selective activation of one or more corresponding wordlines (having the same row address) of memory cell array blocks of a memory cell array to thereby change the page length according to a specified operational mode.

Abstract: A circuit for receiving data to be written in a synchronous semiconductor memory device, comprising: a first set of latches for receiving an n-bit data upon transition of an internal strobe signal; a counter for counting the number of transitions of the internal strobe signal and for outputting an indicating signal upon counting the end of a string of internal strobe signals; a second set of latches for receiving the outputs of the first set of latches, the second set of latches being clocked by the indicating signal; and a third set of latches for receiving the outputs of the second set of latches, the third set of latches being clocked by a clock signal derived from a system clock.

Abstract: Embodiments of the invention provide a command decoder and related circuitry for use in a semiconductor memory device that can operate both as a double rate synchronous dynamic random access random access memory device, and a fast cycle random access memory device.

Abstract: Integrated circuit memory devices include a memory cell array that is configured to write N data bits in parallel and a write data path that is configured to serially receive 2N data bits from an external terminal. The write data path includes 2N write data buffers that are configured to store the 2N data bits, 2N switches, and N data lines that are configured to connect at least N of the 2N switches to the memory cell array to write therein N data bits in parallel. A reduced number of local data lines and/or global data lines may be provided.

Abstract: Data can be buffered for an integrated circuit memory device by converting a plurality of serial data bits into a parallel format such that even ones of the plurality of serial data bits are provided at a first conversion output node and odd ones of the plurality of serial data bits are provided at a second conversion output node wherein a first odd data bit, a first even data bit, a second odd data bit, and a second even data bit comprise four consecutive data bits of the plurality of serial data bits. The first even and odd data bits from the first and second conversion output nodes are provided at first and second latch output nodes during a first period of time, and the second even and odd data bits from the first and second conversion output nodes are provided at third and fourth latch output nodes during a second period of time wherein the first and second periods of time are non-overlapping.

Abstract: The present invention involves a synchronous semiconductor memory device having a 4-bit prefetch mode a method of processing a data thereof, comprising first to fourth memory cell arrays each having memory cells, a serial-parallel converting means converting a plurality of 4-bit data serially applied during a write operation into a plurality of 4-bit parallel data, a data loation control means location-controlling and outputting each of the plurality of the 4-bit parallel data output from the serial-parallel converting means in response first to fourth decoding signals generated by decoding the 2-bit column address to the first to fourth memory cell arrays, by a sequential method or by an interleaving method, during the write operation, a sense amplifier amplifying a plurality of 4-bit data output from each of the first to fourth memory cell arrays, and location-controlling and outputting them in response the first to fourth decoding signals, by a sequential method or by an interleaving method, during a read

Abstract: In a prefetch-type FCRAM having an improved data write control circuit and a method of masking data using the prefetch-type FCRAM, the prefetch-type FCRAM includes a command decoder, a row decoder, a column decoder, a data input buffer, a data output buffer, and a valid write window buffer. The command decoder outputs control commands including first and second write commands in response to predetermined external input signals. The row decoder decodes a row address signal input into the address pins and activates a wordline of the memory cell array corresponding to the decoded row address signal. The column decoder decodes a column address signal input into the address pins and activates a column select line of the memory cell array corresponding to the decoded column address signal. The data input buffer receives input data from the plurality of data pins and then outputs the input data in synchronization with a predetermined clock signal.

Abstract: A semiconductor memory device having an architecture that allows a user to change a page length of the semiconductor device. Circuits and methods for changing a page length of a semiconductor device enable selective activation of one or more corresponding wordlines (having the same row address) of memory cell array blocks of a memory cell array to thereby change the page length according to a specified operational mode.

Abstract: A circuit for receiving data to be written in a synchronous semiconductor memory device, comprising: a first set of latches for receiving an n-bit data upon transition of an internal strobe signal; a counter for counting the number of transitions of the internal strobe signal and for outputting an indicating signal upon counting the end of a string of internal strobe signals; a second set of latches for receiving the outputs of the first set of latches, the second set of latches being clocked by the indicating signal; and a third set of latches for receiving the outputs of the second set of latches, the third set of latches being clocked by a clock signal derived from a system clock.

Abstract: Data can be buffered for an integrated circuit memory device by converting a plurality of serial data bits into a parallel format such that even ones of the plurality of serial data bits are provided at a first conversion output node and odd ones of the plurality of serial data bits are provided at a second conversion output node wherein a first odd data bit, a first even data bit, a second odd data bit, and a second even data bit comprise four consecutive data bits of the plurality of serial data bits. The first even and odd data bits from the first and second conversion output nodes are provided at first and second latch output nodes during a first period of time, and the second even and odd data bits from the first and second conversion output nodes are provided at third and fourth latch output nodes during a second period of time wherein the first and second periods of time are non-overlapping.

Abstract: The present invention provides a dual data rate (DDR) integrated circuit memory device that is configured to support an N to 2N prefetch-to-burst length mode of operation. The DDR integrated circuit memory device is further configured to support a sequential address increase scheme and an interleave address increase scheme.

Abstract: Embodiments of the invention provide a command decoder and related circuitry for use in a semiconductor memory device that can operate both as a double rate synchronous dynamic random access random access memory device, and a fast cycle random access memory device.

Abstract: The present invention involves a synchronous semiconductor memory device having a 4-bit prefetch mode a method of processing a data thereof, comprising first to fourth memory cell arrays each having memory cells, a serial-parallel converting means converting a plurality of 4-bit data serially applied during a write operation into a plurality of 4-bit parallel data, a data loation control means location-controlling and outputting each of the plurality of the 4-bit parallel data output from the serial-parallel converting means in response first to fourth decoding signals generated by decoding the 2-bit column address to the first to fourth memory cell arrays, by a sequential method or by an interleaving method, during the write operation, a sense amplifier amplifying a plurality of 4-bit data output from each of the first to fourth memory cell arrays, and location-controlling and outputting them in response the first to fourth decoding signals, by a sequential method or by an interleaving method, during a read

Abstract: A synchronous semiconductor memory device satisfying the CAS function requirement of JEDEC is provided. Through command input pins and address input pins, external command signals and address signals are applied. A command decoder decodes the applied command signals. A write command latency control unit, a read command latency control unit, and a column address latency control unit delay a write command, a read command, and a column address signal, respectively, for a time period equal to N/2 times a clock signal cycle in response to a latency control signal. N is an integer equal to or greater than zero, and the latency control signal is activated in response to a value set in an extended mode register set.

Abstract: A circuit for receiving data to be written in a synchronous semiconductor memory device, comprising: a first set of latches for receiving an n-bit data upon transition of an internal strobe signal; a counter for counting the number of transitions of the internal strobe signal and for outputting an indicating signal upon counting the end of a string of internal strobe signals; a second set of latches for receiving the outputs of the first set of latches, the second set of latches being clocked by the indicating signal; and a third set of latches for receiving the outputs of the second set of latches, the third set of latches being clocked by a clock signal derived from a system clock.