Abstract: A circuit for through silicon via (TSV) detection includes a TSV to be tested, an equivalent adjustable resistor and a reverse output circuit. A first terminal of the TSV to be tested is connected to a second terminal of the equivalent adjustable resistor, and a second terminal of the TSV to be tested is grounded. An input terminal of the reverse output circuit is connected to the first terminal of the TSV to be tested. The method includes: adjusting a resistance value of the equivalent adjustable resistor to a preset first resistance value, and keeping a voltage of a first terminal of the equivalent adjustable resistor at a preset voltage value, the first resistance value is a maximum resistance value of an equivalent resistor corresponding to the TSV to be tested when the TSV to be tested is normal.

Abstract: A memory array detection circuit includes: a memory array including multiple memory cells; a write circuit, connected to the memory array and configured to write same initial data into each memory cell of the memory array; a read circuit, connected to the memory array and configured read the data stored in each memory cell of the memory array; and a data compression circuit, connected to the read circuit and configured to: compare the data read from the multiple memory cells, and detect whether the memory array is defective according to whether the read data are identical.

Abstract: A memory array detection circuit includes: a memory array including multiple memory cells; a write circuit, connected to the memory array and configured to write same initial data into each memory cell of the memory array; a read circuit, connected to the memory array and configured read the data stored in each memory cell of the memory array; and a data compression circuit, connected to the read circuit and configured to: compare the data read from the multiple memory cells, and detect whether the memory array is defective according to whether the read data are identical.

Abstract: A bandgap voltage reference core circuit includes: a generating circuit, a first voltage dividing circuit and a second voltage dividing circuit. The generating circuit is configured to generate a positive temperature coefficient voltage and a negative temperature coefficient voltage, and obtain a positive temperature coefficient current and a negative temperature coefficient current based on the positive temperature coefficient voltage and the negative temperature coefficient voltage. The first voltage dividing circuit is connected to the generating circuit and the second voltage dividing circuit respectively, and is configured to generate an initial current based on the positive temperature coefficient current and the negative temperature coefficient current. The second voltage dividing circuit is configured to determine a reference voltage based on the initial current. The first voltage dividing circuit and the second voltage dividing circuit affect a voltage dividing proportion of the reference voltage.

Abstract: A circuit for through silicon via (TSV) detection includes a TSV to be tested, an equivalent adjustable resistor and a reverse output circuit. A first terminal of the TSV to be tested is connected to a second terminal of the equivalent adjustable resistor, and a second terminal of the TSV to be tested is grounded. An input terminal of the reverse output circuit is connected to the first terminal of the TSV to be tested. The method includes: adjusting a resistance value of the equivalent adjustable resistor to a preset first resistance value, and keeping a voltage of a first terminal of the equivalent adjustable resistor at a preset voltage value, the first resistance value is a maximum resistance value of an equivalent resistor corresponding to the TSV to be tested when the TSV to be tested is normal.

Abstract: The present disclosure provides a storage device, including: at least one first storage region, at least one drive module, and at least one amplification module. The drive module is arranged on both sides of each of the first storage regions in a word line direction, and the amplification module is arranged on both sides of each of the first storage regions in a bit line direction. Each of the first storage regions includes at least one hybrid storage block arranged side by side in the word line direction and configured to store data and an on die error correcting code (OD-ECC).

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

Abstract: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

Abstract: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.

Abstract: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

Abstract: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.

Abstract: A level translator includes an NMOS input transistor and a PMOS input transistor having respective gates receiving an input voltage. The input transistors compare the input voltage to respective first and second supply voltages. The input voltage is also applied to an inverter that is powered by the first and second supply voltages. An output terminal is coupled to a third supply voltage through a PMOS output transistor and to a fourth supply voltage through an NMOS output transistor. The third and fourth supply voltages are outside of a range bounded by the first and second supply voltages. The respective drains of the input transistors and the output of the inverter are coupled to the gates of the output transistors in a manner that either turns the PMOS output transistor ON and the NMOS output transistor OFF or turns the NMOS output transistor ON and the PMOS output transistor OFF.