Patents by Inventor Onur Mutlu

Onur Mutlu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090031314
    Abstract: Architecture for a multi-threaded system that applies fairness to thread memory request scheduling such that access to the shared memory is fair among different threads and applications. A fairness scheduling algorithm provides fair memory access to different threads in multi-core systems, thereby avoiding unfair treatment of individual threads, thread starvation, and performance loss caused by a memory performance hog (MPH) application. The thread slowdown is determined by considering the thread's inherent memory-access characteristics, computed as the ratio of the real latency that the thread experiences and the latency (ideal latency) that the thread would have experienced if it had run as the only thread in the same system. The highest and lowest slowdown values are then used to generate an unfairness parameter which when compared to a threshold value provides a measure of fairness/unfairness currently occurring in the request scheduling process.
    Type: Application
    Filed: July 25, 2007
    Publication date: January 29, 2009
    Applicant: MICROSOFT CORPORATION
    Inventors: Thomas Moscibroda, Onur Mutlu
  • Publication number: 20040199731
    Abstract: A method and apparatus for accessing memory comprising monitoring memory accesses from a hardware prefetcher; determining whether the memory accesses from the hardware prefetcher are used by an out-of-order core; and switching memory accesses from a first mode to a second mode if a percentage of the memory access generated by the hardware prefetcher are used by the out-of-order core.
    Type: Application
    Filed: April 19, 2004
    Publication date: October 7, 2004
    Inventors: Eric A. Sprangle, Onur Mutlu
  • Patent number: 6799257
    Abstract: A method and apparatus for accessing memory comprising monitoring memory accesses from a hardware prefetcher and determining whether the memory accesses from the hardware prefetcher are used by an out-of-order core. A front side bus controller switches memory access modes from a minimize memory access latency mode to a maximize memory bus bandwidth mode if a percentage of the memory accesses generated by the hardware prefetcher are used by the out-of-order core.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: September 28, 2004
    Assignee: Intel Corporation
    Inventors: Eric A. Sprangle, Onur Mutlu
  • Publication number: 20040128448
    Abstract: Processor architectures, and in particular, processor architectures with a cache-like structure to enable memory communication during runahead execution. In accordance with an embodiment of the present invention, a system including a memory; and an out-of-order processor coupled to the memory. The out-of-order processor including at least one execution unit, at least one cache coupled to the at least one execution unit; at least one address source coupled to the at least one cache; and a runahead cache coupled to the at least one address source.
    Type: Application
    Filed: December 31, 2002
    Publication date: July 1, 2004
    Applicant: INTEL CORPORATION
    Inventors: Jared W. Stark, Chris B. Wilkerson, Onur Mutlu
  • Publication number: 20030159008
    Abstract: A method and apparatus for accessing memory comprising monitoring memory accesses from a hardware prefetcher; determining whether the memory accesses from the hardware prefetcher are used by an out-of-order core; and switching memory accesses from a first mode to a second mode if a percentage of the memory access generated by the hardware prefetcher are used by the out-of-order core.
    Type: Application
    Filed: February 21, 2002
    Publication date: August 21, 2003
    Inventors: Eric A. Sprangle, Onur Mutlu