Abstract: Provided is an early electromagnetic wave abnormality detection device in which a frequency detector including a fast response rate and a function of classifying electromagnetic waves and generating a warning signal by analyzing the detection signal are embedded in a single chip device, whereby an electromagnetic wave abnormality is detected early. A receiving end receives an antenna signal from an antenna block and generates a conversion signal. A switch changes a gain according to characteristics of the antenna signal and generates the conversion signal. A frequency power detector generates frequency information and power information using the conversion signal. A symptom detector generates determination information for determining an early electromagnetic wave abnormality using the frequency information and the power information. An MCU executes one of a plurality of control modes to control the operation of at least one of the receiving end and the switch according to the determination information.

Abstract: A device for detecting electromagnetic wave abnormality using a neural network, in which defects of a system may be prevented by detecting and reporting a premonitory symptom of abnormality of a system based on electromagnetic characteristics during a normal operation, includes a reception end portion configured to receive at least one antenna signal from an antenna block and generate at least one converted signal, a switch configured to change a gain according to characteristics of the at least one antenna signal and perform switching to generate the at least one converted signal, a frequency power detector configured to generate frequency information and power information using the at least one converted signal, and a symptom detector configured to generate electromagnetic wave symptom classification information by applying the frequency information and the power information as input data to a neural network.

Abstract: An electromagnetic wave detection device in which a frequency detector including a fast response rate and a function of classifying electromagnetic waves and generating a warning signal are embedded in a single chip device. The electromagnetic wave detection device includes a receiving end portion configured to receive at least one antenna signal from an antenna block and generate at least one conversion signal, a switch configured to perform switching to change a gain according to characteristics of the at least one antenna signal and generate the at least one conversion signal, a frequency power detector configured to generate frequency information and power information using the at least one conversion signal, and a symptom detector configured to classify an electromagnetic wave using the frequency information and the power information.

Abstract: A memory device for controlling an asynchronous FIFO memory of an asymmetric data width is disclosed. A memory device according to one embodiment includes a First-in, First-out (FIFO) memory where data is input and output, an address counter that controls writing and reading of the FIFO memory, an address pointer generator that is capable of comparing a write clock domain and a read clock domain for checking a status of the FIFO memory, and a flag generator that outputs the status of the FIFO memory based on a comparison of address pointers generated by the address pointer generator, wherein a write data width and a read data width are differently processed in the FIFO memory.

Abstract: The present invention provides a circuit for generating a bias voltage for a high speed input/output pad. To this end, a bias voltage generator according to an embodiment of the present invention is to supply at least one bias voltage to a buffer circuit connected to the pad, which includes: a bias generation part for generating a first bias voltage; and a reference voltage generation part for generating a voltage proportional to the pad voltage applied to the pad as a reference voltage, wherein the first bias voltage may be the sum of the reference voltage and a predetermined voltage.

Abstract: The present invention provides a circuit for generating a bias voltage for a high speed input/output pad. To this end, a bias voltage generator according to an embodiment of the present invention is to supply at least one bias voltage to a buffer circuit connected to the pad, which includes: a bias generation part for generating a first bias voltage; and a reference voltage generation part for generating a voltage proportional to the pad voltage applied to the pad as a reference voltage, wherein the first bias voltage may be the sum of the reference voltage and a predetermined voltage.

Abstract: A method, apparatus and system for pre-authenticating ports is disclosed. In one embodiment, an active port facilitating communication of media content between a transmitting device and a receiving device is identified, while the active port are associated with a first High-Definition Content Protection (HDCP) engine. Then, inactive ports that are in idle mode serving as backup ports to the active port are identified, while the inactive ports are associated with a second HDCP engine. Pre-authentication of each of the inactive ports is performed so the pre-authenticated inactive ports can subsequently replace the active port if a port switch is performed.

Abstract: Disclosed are an apparatus (equalizer module or receiving apparatus) of a high speed interface system and a high speed interface system, in which the resistance value of a termination resistor in a circuit for high speed interface is adjusted to follow that of a termination resistor of a sink circuit unit, thereby implementing efficient equalization and high speed interface, and a command bus (CBUS) is not built in an equalizer integrated circuit (IC), so that it is possible to simplify the configuration of the high speed interface system and improve the performance and efficiency of the high speed interface system.

Abstract: The present specification provides a cable and a compensation method for transmitting a high speed signal and delivering power. The cable according to one embodiment disclosed in the present specification interconnects a first device and a second device, the cable comprising: a power line for transmitting power from the first device to the second device; and a voltage restorer for restoring voltage loss of the power receiving side of the second device generated based on the voltage drop relevant to the power line.

Abstract: Transmission of alternative content over standard device connectors. An embodiment of a method includes connecting a first device to a second device utilizing a standard connector, the connector including multiple pins, and detecting whether the second device is operating in a standard mode or an alternative mode. If the second device is operating in the alternative mode, then switching one or more pins of the standard connector for the alternative mode and transmitting or receiving signals for the alternative mode via the plurality of pins of the standard connector.

Abstract: Transmission of alternative content over standard device connectors. An embodiment of a method includes connecting a first device to a second device utilizing a standard connector, the connector including multiple pins, and detecting whether the second device is operating in a standard mode or an alternative mode. If the second device is operating in the alternative mode, then switching one or more pins of the standard connector for the alternative mode and transmitting or receiving signals for the alternative mode via the plurality of pins of the standard connector.

Abstract: Methods and apparatuses for using single-ended common mode signaling, additional data can be transferred in backward, forward, and/or both directions over an existing differential pair connection without adding extra wire.

Abstract: A method, apparatus and system for pre-authenticating ports is disclosed. In one embodiment, an active port facilitating communication of media content between a transmitting device and a receiving device is identified, while the active port are associated with a first High-Definition Content Protection (HDCP) engine. Then, inactive ports that are in idle mode serving as backup ports to the active port are identified, while the inactive ports are associated with a second HDCP engine. Pre-authentication of each of the inactive ports is performed so the pre-authenticated inactive ports can subsequently replace the active port if a port switch is performed.

Abstract: In preferred embodiments, an adaptive equalization circuit including at least two equalization filters (each for equalizing a signal transmitted over a multi-channel serial link) and control circuitry for generating an equalization control signal for use by all the filters. The control circuitry generates the control signal in response to an equalized signal produced by one of the filters, and asserts the control signal to all the filters. Preferably, one filter generates an equalized fixed pattern signal in response to a fixed pattern signal (e.g., a clock signal), each other filter equalizes a data signal, and the control circuitry generates the control signal in response to the equalized fixed pattern signal.

Abstract: A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information.

Abstract: A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information.

Abstract: A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information.

Abstract: The present invention relates to a method for exposing an edge of a semiconductor wafer in photolithographic processes, and an OF (Orientation Flatness) detecting system provided with a WEE (Wafer Edge Exposure) apparatus. According to the present invention, a notch-aligned wafer can be treated by a WEE process on a wafer chuck of an OF detecting system, without waiting for its patterning exposure process to be performed first. Thus, the total processing time in photolithographic processes can be decreased.

Abstract: A method of transmitting data in a system including at least one data channel and a separate clock channel is disclosed. The method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least one edge (i.e. front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.

Abstract: A scheme for reducing jitter in high-speed digital communication by adaptively controlling the loop bandwidth of a receiver PLL to reduce the relative jitter between the recovered data and clock. The scheme uses phase pointer activity to represent the relative jitter. The phase pointer activity is measured and used to control the receiver PLL loop bandwidth. The receiver PLL loop bandwidth is repeatedly incremented or decremented by a step size based on the comparison between a newly measured activity value and the old activity value, until the phase pointer activity reaches a minimum. Because the PLL performance requirement of the transmitter can be relaxed, compatibility with legacy transmitters and multi-vendor transmitters is enhanced. Because tight control of fabrication process parameters of PLLs may be relaxed, the fabrication yield may also be improved.