Abstract: In an embodiment, a system includes a plurality of integrated circuits have subsets of a plurality of agents. The plurality of integrated circuits may have network segments implemented wholly (e.g., entirely) within the respective integrated circuits and may have segment to segment (S2S) network interface circuits to couple to other network segments of a plurality of network segment forming a network among the plurality of agents.

Abstract: According to an embodiment of the present invention, a microprocessor includes an expanded logical register set that can be accessed by instructions including legacy opcodes and remapped addressing mode information. The known IA-32 instruction set is limited to accessing eight logical general integer registers. An IA-32 instruction can specify which of the eight logical general integer registers are to be accessed via 3-bit register identifier fields of the addressing mode information of the instruction. Each 3-bit register identifier can specify any of the eight logical general integer registers. An expanded logical register set (e.g., sixteen logical registers, thirty-two logical registers, sixty-four logical registers, etc.) can be accessed by remapping the addressing mode information to include at least four-bit register identifiers without defining new opcodes or defining additional instruction prefixes.

Abstract: A circuit includes a switch unit, an non-protected register and a set of protected control registers. The set of protected control registers stores safe data for use by another unit of the circuit. The switch unit outputs the data stored by one of the set of protected control registers as a function of the data stored by the non-protected register. The data in the non-protected register can be changed by software in response to user input, operational mode or other condition or conditions.

Abstract: A memory controller (MC) includes a buffer control circuit (BCC) to enable/disable buffer coupled to a terminated bus. The BCC can detect transactions and speculatively enable the buffers before the transaction is completely decoded. If the transaction is targeted for the terminated bus, the buffers will be ready to drive signals onto the terminated bus by the time the transaction is ready to be performed, thereby eliminating the “enable buffer” delay incurred in some conventional MCs. If the transaction is not targeted for the terminated bus, the BCC disables the buffers to save power. In MCs that queue transactions, the BCC can snoop the queue to find transactions targeted for the terminated bus and begin enabling the buffers before these particular transactions are fully decoded.

Abstract: One or more memory requests are stored in a request buffer. Each memory request targets a memory device in a memory system having one or more memory devices. Each memory device has a first power state and a second power state. Each memory request is issued in an order from the request buffer to the memory system. The memory device targeted by one memory request from the request buffer is identified prior to or while another memory request ahead of the one memory request is issued to the memory system and performed by the memory system. The identified memory device is placed or maintained in the second power state prior to issuing the one memory request to the memory system.

Abstract: A method for dynamically adjusting a memory page-closing policy for computer systems employing various types of DRAM memory partitioned into one or more memory banks, and circuitry for implementing the method. In general, the method comprises monitoring memory accesses to memory banks and dynamically adjusting the memory page closing policy for those memory bank based on locality characteristics of its memory accesses so that memory latencies are reduced. In one embodiment, in response to memory requests from a computer system processor, memory accesses to the DRAM memory are made on a page-wise basis. As each memory page is accessed, a page-miss, page-hit or page-hit state is produced. Depending on the page access states, which generally will reflect the locality characteristics of (an) application(s) accessing the memory, a page-close set point is adjusted. When a timing count corresponding to the page exceeds the page-close set point, the memory page is closed.

Abstract: The present invention relates to a method and system for providing a load with conditional fault instruction that includes an associated conditional operator, which enables load operations to be advanced above program branches by the compiler without causing unwarranted fault conditions. Specifically, the load instruction can be executed out of normal program order to enable information to be retrieved from memory before the information is needed, to permit the retrieved information to begin to be used before the conditional operator can be evaluated. Likewise, a dynamically scheduled processor can advance components of the instruction and further improve performance without having faults effect the normal program flow. The load instruction can stop the use of the information and replace the information with a predetermined, generally deterministic, value if the conditional operator indicates a faulty load operation.

Abstract: Method for producing a predetermined length page memory pointer record, according to a selected page size and a selected page address, the method including the procedures of: determining a dynamic location of a separator bit within the page memory pointer record, according to the selected page size and an initial page size, the initial page size being respective of the smallest page size in a given memory system, writing a predetermined value to the dynamic location, writing a sequence of values opposite to the predetermined value to selected page size bits of the page memory pointer record, when the selected page size is different than the initial page size, and writing the selected page address to selected page address bits of the page memory pointer record.

Abstract: Method for producing a predetermined length page memory pointer record, according to a selected page size and a selected page address, the method including the procedures of: determining a dynamic location of a separator bit within the page memory pointer record, according to the selected page size and an initial page size, the initial page size being respective of the smallest page size in a given memory system, writing a predetermined value to the dynamic location, writing a sequence of values opposite to the predetermined value to selected page size bits of the page memory pointer record, when the selected page size is different than the initial page size, and writing the selected page address to selected page address bits of the page memory pointer record.

Abstract: A memory controller (MC) includes a buffer control circuit (BCC) to enable/disable buffer coupled to a terminated bus. The BCC can detect transactions and speculatively enable the buffers before the transaction is completely decoded. If the transaction is targeted for the terminated bus, the buffers will be ready to drive signals onto the terminated bus by the time the transaction is ready to be performed, thereby eliminating the “enable buffer” delay incurred in some conventional MCs. If the transaction is not targeted for the terminated bus, the BCC disables the buffers to save power. In MCs that queue transactions, the BCC can snoop the queue to find transactions targeted for the terminated bus and begin enabling the buffers before these particular transactions are fully decoded.

Abstract: Method for producing a predetermined length page memory pointer record, according to a selected page size and a selected page address, the method including the procedures of: determining a dynamic location of a separator bit within the page memory pointer record, according to the selected page size and an initial page size, the initial page size being respective of the smallest page size in a given memory system, writing a predetermined value to the dynamic location, writing a sequence of values opposite to the predetermined value to selected page size bits of the page memory pointer record, when the selected page size is different than the initial page size, and writing the selected page address to selected page address bits of the page memory pointer record.

Abstract: Processors and methods having an expanded logical register set are disclosed. A processor includes may include Intel Architecture-32 (IA-32) instruction set decoding logic and an expanded logical register set. The expanded logical register set may include more than eight logical registers of a first type. An expanded register set decoding logic, coupled to said IA-32 instruction set decoding logic, may determine that an instruction includes an at least four-bit register identifier, the at least four-bit register identifier to specify one logical register of said expanded logical register set.

Abstract: A memory controller, in one embodiment of the present invention, can control the execution of a memory maintenance operation. A screen blanking event counter can output a first signal. A memory maintenance state circuit can be coupled to the screen blanking event counter to receive the first signal. The memory maintenance state circuit can output a memory maintenance enable signal.

Abstract: A method for dynamically adjusting a memory page-closing policy for computer systems employing various types of DRAM memory partitioned into one or more memory banks, and circuitry for implementing the method. In general, the method comprises monitoring memory accesses to memory banks and dynamically adjusting the memory page closing policy for those memory bank based on locality characteristics of its memory accesses so that memory latencies are reduced. In one embodiment, in response to memory requests from a computer system processor, memory accesses to the DRAM memory are made on a page-wise basis. As each memory page is accessed, a page-miss, page-hit or page-hit state is produced. Depending on the page access states, which generally will reflect the locality characteristics of (an) application(s) accessing the memory, a page-close set point is adjusted. When a timing count corresponding to the page exceeds the page-close set point, the memory page is closed.

Abstract: A circuit includes a switch unit, an non-protected register and a set of protected control registers. The set of protected control registers stores safe data for use by another unit of the circuit. The switch unit outputs the data stored by one of the set of protected control registers as a function of the data stored by the non-protected register. The data in the non-protected register can be changed by software in response to user input, operational mode or other condition or conditions.

Abstract: One or more memory requests are stored in a request buffer. Each memory request targets a memory device in a memory system having one or more memory devices. Each memory device has a first power state and a second power state. Each memory request is issued in an order from the request buffer to the memory system. The memory device targeted by one memory request from the request buffer is identified prior to or while another memory request ahead of the one memory request is issued to the memory system and performed by the memory system. The identified memory device is placed or maintained in the second power state prior to issuing the one memory request to the memory system.

Abstract: It is determined whether one or more memory devices coupled with each output of one or more output buffers by a terminated bus are in a first power state or a second power state. Each output buffer has a first impedance state and a second impedance state. The one or more output buffers are placed or maintained in the first impedance state in response to determining each of the one or more memory devices is in the first power state.

Abstract: The present invention relates to a method and system for providing a load with conditional fault instruction that includes an associated conditional operator, which enables load operations to be advanced above program branches by the compiler without causing unwarranted fault conditions. Specifically, the load instruction can be executed out of normal program order to enable information to be retrieved from memory before the information is needed, to permit the retrieved information to begin to be used before the conditional operator can be evaluated. Likewise, a dynamically scheduled processor can advance components of the instruction and further improve performance without having faults effect the normal program flow. The load instruction can stop the use of the information and replace the information with a predetermined, generally deterministic, value if the conditional operator indicates a faulty load operation.

Abstract: A computer system provides enhanced performance when executing irregular code that include pointer de-reference operations. A memory controller of the computer system first fetches a pointer value from an address location in the memory and then calculates a new address adding a constant or scale factor to the pointer value. A logical-to-physical (i.e., virtual-to-physical) translation of the pointer value is also performed. The loading of data for the initial pointer load operation is overlapped with the de-reference operation, wherein the de-reference data is prefetched from memory using the resulting address and placed into the CPU's cache.