Abstract: The present disclosure relates to systems and methods for communicating between devices using short-range communication links. More specifically, the present disclosure relates to systems and methods for communicating access-right data between devices for verification or transfer.

Abstract: A non-volatile memory has an array of non-volatile memory cells, first reference word lines and second reference word lines, and sense amplifiers. The sense amplifiers read system data, that has been written to supplemental non-volatile memory cells of the first reference word lines, using comparison of the supplemental non-volatile memory cells of the first reference word lines to supplemental non-volatile memory cells of the second reference word lines. Status of erasure of the non-volatile memory cells of the array is determined based on reading the system data.

Abstract: A duplexer includes a cavity resonator defining an opening covered by an RF plate. The RF plate defines an opening through which a pass-band tuning pipe extends and is secured thereto. A collar is attached to one end of the pipe, and at least one steel set screw extends into the interior of the collar, the at least one end having a soft (e.g., brass) tip. A tuning plunger is slidingly positioned within the pass-band tuning pipe. A rod is attached to a first end of the tuning plunger and extends through the collar, the rod being fabricated from a material harder than the tip of the at least one set screw. The at least one set screw is configured for tightening down on the rod to secure the rod and tuning plunger in place. A trimmer capacitor is positioned in the RF plate.

Abstract: Novel and useful system and methods of functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The NN processor incorporates functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well. The safety mechanisms cover data stream fault detection, software defined redundant allocation, cluster interlayer safety, cluster intralayer safety, layer control unit (LCU) instruction addressing, weights storage safety, and neural network intermediate results storage safety.

Abstract: Provided herewith a computer-based method for assessing a location of an object-of-interest (OBIN) in a building site. The method may comprise: acquiring an image of an OBIN captured by an image capturing device (ICD) within the building site; acquiring a position and orientation of the ICD at the time the image was captured; processing the image to identify an observed reference point of the OBIN on the image; and determining spatial coordinates for the observed reference point with respect to the model. Alternatively, the method may comprise: acquiring an image of a building site captured by an ICD; acquiring a position and orientation of the ICD at the time the image was captured; determining an expected position on the image for an object based on a model of the building site; determining an image-based-position of the object; and detecting a discrepancy between the expected position and the image-based position.

Abstract: Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The mechanisms address ANN system level safety in situ, as a system level strategy tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts that function to detect and promptly flag and report an error with some mechanisms capable of correction as well.

Abstract: The present disclosure relates to systems and methods for communicating between devices using short-range communication links. More specifically, the present disclosure relates to systems and methods for communicating access-right data between devices for verification or transfer.

Abstract: A method of operating a memory device includes: supplying one or more supply voltages to a memory array; and monitoring the one or more supply voltages, which includes: selecting, from the one or more supply voltages, a selected supply voltage; converting, using an analog-to-digital converter (ADC), an internal reference voltage of the memory device and a scaled version of the selected supply voltage into one or more digital values; generating a calibrated measurement result using the one or more digital values; and determining whether the calibrated measurement result is within a pre-determined range.

Abstract: A method of generating an interactive graphical user interface (GUI), comprising: receiving one or more images captured by an image sensor of a mobile device in a construction site, each image is associated with one or more positioning parameter indicative of the mobile device’s position when the respective image is captured, rendering the image(s) on a display, receiving user input indicating selection of an area in the image(s) depicting a corresponding area in the construction site, accessing a 3D model documenting construction task status relating to each of a plurality of elements in the construction site, registering the image(s) to the 3D model according to the positioning parameter(s) to identify, in the selected area, elements documented in the 3D model, retrieving a respective construction task status relating to the identified elements; and adapting a GUI presented in association with the selected area according to the respective construction task status.

Abstract: Radiation detecting-structures and fabrications methods thereof are presented. The methods include, for instance: providing a substrate, the substrate including at least one trench extending into the substrate from an upper surface thereof; and epitaxially forming a radiation-responsive semiconductor material layer from one or more sidewalls of the at least one trench of the substrate, the radiation-responsive semiconductor material layer responding to incident radiation by generating charge carriers therein. In one embodiment, the sidewalls of the at least one trench of the substrate include a (111) surface of the substrate, which facilitates epitaxially forming the radiation-responsive semiconductor material layer. In another embodiment, the radiation-responsive semiconductor material layer includes hexagonal boron nitride, and the epitaxially forming includes providing the hexagonal boron nitride with an a-axis aligned parallel to the sidewalls of the trench.

Abstract: The present disclosure relates to systems and methods for communicating between devices using short-range communication links. More specifically, the present disclosure relates to systems and methods for communicating access-right data between devices for verification or transfer.

Abstract: A novel and useful neural network (NN) processing core incorporating inter-device connectivity and adapted to implement artificial neural networks (ANNs). A chip-to-chip interface spreads a given ANN model across multiple devices in a seamless manner. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level.

Abstract: A non-volatile memory has an array of non-volatile memory cells, first reference word lines and second reference word lines, and sense amplifiers. The sense amplifiers read system data, that has been written to supplemental non-volatile memory cells of the first reference word lines, using comparison of the supplemental non-volatile memory cells of the first reference word lines to supplemental non-volatile memory cells of the second reference word lines. Status of erasure of the non-volatile memory cells of the array is determined based on reading the system data.

Abstract: A novel and useful system and method of improved power performance and lowered memory requirements for an artificial neural network based on packing memory utilizing several structured sparsity mechanisms. The invention applies to neural network (NN) processing engines adapted to implement mechanisms to search for structured sparsity in weights and activations, resulting in a considerably reduced memory usage. The sparsity guided training mechanism synthesizes and generates structured sparsity weights. A compiler mechanism within a software development kit (SDK), manipulates structured weight domain sparsity to generate a sparse set of static weights for the NN. The structured sparsity static weights are loaded into the NN after compilation and utilized by both the structured weight domain sparsity mechanism and the structured activation domain sparsity mechanism.

Abstract: A novel and useful system and method of improved power performance and lowered memory requirements for an artificial neural network based on packing memory utilizing several structured sparsity mechanisms. The invention applies to neural network (NN) processing engines adapted to implement mechanisms to search for structured sparsity in weights and activations, resulting in a considerably reduced memory usage. The sparsity guided training mechanism synthesizes and generates structured sparsity weights. A compiler mechanism within a software development kit (SDK), manipulates structured weight domain sparsity to generate a sparse set of static weights for the NN. The structured sparsity static weights are loaded into the NN after compilation and utilized by both the structured weight domain sparsity mechanism and the structured activation domain sparsity mechanism.

Abstract: A novel and useful system and method of improved power performance and lowered memory requirements for an artificial neural network based on packing memory utilizing several structured sparsity mechanisms. The invention applies to neural network (NN) processing engines adapted to implement mechanisms to search for structured sparsity in weights and activations, resulting in a considerably reduced memory usage. The sparsity guided training mechanism synthesizes and generates structured sparsity weights. A compiler mechanism within a software development kit (SDK), manipulates structured weight domain sparsity to generate a sparse set of static weights for the NN. The structured sparsity static weights are loaded into the NN after compilation and utilized by both the structured weight domain sparsity mechanism and the structured activation domain sparsity mechanism.

Abstract: A novel and useful neural network (NN) processing core adapted to implement artificial neural networks (ANNs) and incorporating processing circuits having compute and local memory elements. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level.

Abstract: A system for physiological measurement of a physiological process of a body of a patient, the system comprising: at least one physiological sensor operable to collect, at a plurality of different times during a physiological measurement, physiological data from the body of the patient, the physiological data resulting at least from the physiological process; and a processor operable to: (a) determine many-valued quality scores for the physiological data collected at the plurality of different times, and (b) provide an indication that the physiological measurement was successful in response to determining that an accumulative amount of times, out of the plurality of different times, for which the determined many-valued quality score fulfilled a predetermined criterion, exceeded a predetermined amount.

Abstract: Some embodiments of the current invention relate to a 3D scanner that models while scanning. For example, the device may recognize common objects and/or edges while scanning. For example, the scanner may create a boundary representation (B-rep) model as it scans. Optionally, the scanner is configured to take advantage of common features on a specific environment. For example, an indoor building scanner may look for known architectural features, walls, edges, corners, pillars doors and/or windows etc. Optionally, the scanner includes a pan tilt head controlled by a controller to scan key features identified in the modelling. Optionally the scanner is stationary and/or mounted on an autonomous robotic platform. Optionally the controller selects a new position to put the scanner and/or outputs the new position to a user.

Abstract: A novel and useful system and method of accessing multi-dimensional data in memory. The invention is applicable to neural network (NN) processing engines adapted to implement artificial neural networks (ANNs). The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level.