Abstract: A method of statically allocating memory for a computer program includes splitting a computational graph associated with a plurality of static memory allocation constraints into a plurality of subgraphs; determining a memory allocation for each combination of subgraphs of the plurality of subgraphs using an SAT solver and a plurality of Boolean conditions that formalize the plurality of static memory allocation constraints; subdividing a subgraph of the plurality of subgraphs into a plurality of tiles, when the memory allocation for that subgraph cannot satisfy a hardware memory size constraint of the plurality of static memory allocation constraints; performing a performance analysis on all possible subgraphs and plurality of tiles; selecting a combination of subgraphs whose plurality of tiles has a best overall performance; and determining a memory allocation for the plurality of tiles for the selected combination of subgraphs using the SAT solver.

Abstract: A cache writeback circuit is disclosed for writing back, without invalidating, dirty cache lines. The cache writeback circuit is configured to enter an active state based on detecting a trigger condition indicative of cache misses to a memory cache circuit within a memory hierarchy of a computer memory subsystem causing cache line eviction activity. During the active state, the cache writeback circuit is configured to identify a set of dirty cache lines in the memory cache circuit, and write back, without invalidating, cache lines of the identified set of dirty cache lines from the memory cache circuit to a memory circuit within a lower level of the memory hierarchy, such as DRAM. The cache writeback circuit may further be configured to identify the dirty cache lines via a cache walk operation, which can be suspended, for example, when a higher-priority cache operation occurs.

Abstract: The described techniques provide for an automated process of hardware design using main applications (e.g., use cases) and a modeling heuristic of a compiler. Hardware may be optimized and designed based on the knowledge of the compiler for the hardware and firmware information. For instance, a user may define constraints (e.g., area constraints, power constraints, performance constraints, accuracy degradation constraints, etc.) and the changes of compilation heuristics and hardware parameters may be optimized to efficiently achieve the user defined constraints. Accordingly, hardware configuration parameters may be optimized based on the neural network's compilation process (e.g., actual compiler constraints) and optimization of power, performance, and area (PPA) constraints (e.g., user defined constraints). Specific neural processor (SNP) hardware may thus be designed based on the optimized hardware configuration parameters (e.g.

Abstract: A method of statically allocating memory for a computer program includes splitting a computational graph associated with a plurality of static memory allocation constraints into a plurality of subgraphs; determining a memory allocation for each combination of subgraphs of the plurality of subgraphs using an SAT solver and a plurality of Boolean conditions that formalize the plurality of static memory allocation constraints; subdividing a subgraph of the plurality of subgraphs into a plurality of tiles, when the memory allocation for that subgraph cannot satisfy a hardware memory size constraint of the plurality of static memory allocation constraints; performing a performance analysis on all possible subgraphs and plurality of tiles; selecting a combination of subgraphs whose plurality of tiles has a best overall performance; and determining a memory allocation for the plurality of tiles for the selected combination of subgraphs using the SAT solver.

Abstract: Systems and techniques of the present disclosure enable a compiler to optimize such tradeoffs, and further enable optimization for a specific user cost function (e.g., optimization of a complex multi-dimensional and non-linear problem). Moreover, the techniques described herein can optimize in polynomial time. Accordingly, inference tasks may be optimized (e.g., based on specific applications) in terms of power consumption, idle time, the efficiency of computation, system resources, etc. For instance, by leveraging the systems and techniques described in the present disclosure, hardware designers can balance the tradeoff between runtime, power consumption, and resource usage, which are critical factors in the efficient processing of specialized tasks.

Abstract: The described techniques provide for an automated process of hardware design using main applications (e.g., use cases) and a modeling heuristic of a compiler. Hardware may be optimized and designed based on the knowledge of the compiler for the hardware and firmware information. For instance, a user may define constraints (e.g., area constraints, power constraints, performance constraints, accuracy degradation constraints, etc.) and the changes of compilation heuristics and hardware parameters may be optimized to efficiently achieve the user defined constraints. Accordingly, hardware configuration parameters may be optimized based on the neural network's compilation process (e.g., actual compiler constraints) and optimization of power, performance, and area (PPA) constraints (e.g., user defined constraints). Specific neural processor (SNP) hardware may thus be designed based on the optimized hardware configuration parameters (e.g.

Abstract: Embodiments are disclosed for solving a Boolean formula generated from an input design using an iterative loop using a computer-implemented Boolean satisfiability solver. An example method includes accessing data qualifier signals indicating one or more variables in a Boolean formula. The example method further includes marking the one or more variables in the Boolean formula as data qualifier variables based on the respective data qualifier signals. The example method further includes instructing a computer implemented Boolean satisfiability solver to solve the Boolean formula using an iterative loop, where operation of the iterative loop is prioritized based on the data qualifier variables. Corresponding apparatuses and non-transitory computer readable storage media are also provided.

Abstract: An apparatus for IC design includes a memory configured to store an original Register Transfer Level (RTL) model, a corrected RTL model, and a translation of the original RTL model into a netlist. A processor is configured to identify in the original RTL model a flip-flop having a next-state function that is not equivalent to a corresponding next-state function of a corresponding flip-flop in the Corrected RTL model, to find a wire, which is the earliest ancestor of the flip-flop for which there is no equivalence between the original RTL model and the corrected RTL model, to check whether the wire has an equivalent net in the netlist, to identify, upon finding that the wire has no equivalent net, one or more ancestors of the wire, which do have equivalent nets in the netlist, and to modify the netlist to match the corrected RTL model.

Abstract: An apparatus for IC design includes a memory configured to store an original Register Transfer Level (RTL) model, a corrected RTL model, and a translation of the original RTL model into a netlist. A processor is configured to identify in the original RTL model a flip-flop having a next-state function that is not equivalent to a corresponding next-state function of a corresponding flip-flop in the Corrected RTL model, to find a wire, which is the earliest ancestor of the flip-flop for which there is no equivalence between the original RTL model and the corrected RTL model, to check whether the wire has an equivalent net in the netlist, to identify, upon finding that the wire has no equivalent net, one or more ancestors of the wire, which do have equivalent nets in the netlist, and to modify the netlist to match the corrected RTL model.

Abstract: A method for circuit design automation includes receiving an initial RTL definition of a design of a circuit, and synthesizing an initial netlist of the circuit based on the initial RTL definition. After synthesizing the initial netlist, an updated RTL definition containing a design change and a corresponding updated netlist are received. The updated RTL definition and netlist are automatically analyzed to identify first and second logical relations that were changed in the RTL definition and netlist, respectively. A notification is issued of sets of the endpoints between which the first logical relations were changed without changes to the second logical relations or vice versa. For the sets of the endpoints between which both the first logical relations and the second logical relations were changed, the equivalence between the first and second logical relations is automatically verified.

Abstract: Embodiments are disclosed for solving a Boolean formula generated from an input design using an iterative loop using a computer-implemented Boolean satisfiability solver. An example method includes accessing data qualifier signals indicating one or more variables in a Boolean formula. The example method further includes marking the one or more variables in the Boolean formula as data qualifier variables based on the respective data qualifier signals. The example method further includes instructing a computer implemented Boolean satisfiability solver to solve the Boolean formula using an iterative loop, where operation of the iterative loop is prioritized based on the data qualifier variables. Corresponding apparatuses and non-transitory computer readable storage media are also provided.

Abstract: A method for circuit design automation includes receiving an initial RTL definition of a design of a circuit, and synthesizing an initial netlist of the circuit based on the initial RTL definition. After synthesizing the initial netlist, an updated RTL definition containing a design change and a corresponding updated netlist are received. The updated RTL definition and netlist are automatically analyzed to identify first and second logical relations that were changed in the RTL definition and netlist, respectively. A notification is issued of sets of the endpoints between which the first logical relations were changed without changes to the second logical relations or vice versa. For the sets of the endpoints between which both the first logical relations and the second logical relations were changed, the equivalence between the first and second logical relations is automatically verified.

Abstract: A method, computer program, and apparatus are described for finding the logical equivalence between register transfer level (RTL) wires and post synthesis nets in a netlist. In some example embodiments, the method includes minimizing nets in a netlist and matching each RTL wire to a netlist net. In some example embodiments, the method also includes determining if an RTL wire is logically equivalent to a netlist net. In some example embodiments, the method also includes determining a new candidate for a net if the RTL wire and associated netlist net are not logically equivalent.

Abstract: A method, computer program, and apparatus are described for finding the logical equivalence between register transfer level (RTL) wires and post synthesis nets in a netlist. In some example embodiments, the method includes minimizing nets in a netlist and matching each RTL wire to a netlist net. In some example embodiments, the method also includes determining if an RTL wire is logically equivalent to a netlist net. In some example embodiments, the method also includes determining a new candidate for a net if the RTL wire and associated netlist net are not logically equivalent.