Patents by Inventor Or Nahir

Or Nahir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10601591
    Abstract: Systems, methods, and computer-readable storage media are provided for enabling discovery of a user by a member of an inner circle of the member when the user is in close proximity to the member. An indication is received from a user device indicating members of an inner circle of the user. A private key is sent to the mobile devices of each member of the inner circle. When the user device broadcasts an encrypted identifier, member devices with the private key can decrypt the encrypted identifier, allowing the member to discover that the user is in close proximity. The user can also update membership of the inner circle so that only members presently in the inner circle can discover that the user is in close proximity.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: March 24, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Alona Kushnirsky, Haim Somech, Oded Nahir
  • Patent number: 10528443
    Abstract: A method, apparatus and computer program product to be employed by a hardware component under validation, wherein the hardware component having a plurality of processing units each belonging to one of at least two types, such that one of the at least two types of processing units is less error-prone than a remainder of the at least two types. The method comprising: designating one of the processing units of the hardware component under validation that belongs to the less error-prone type as a manager processing unit; initiating execution of a tester program code for testing processing units, by processing units of the hardware component other than the manager processing unit; and, monitoring by the manager processing unit the status of the processing units during execution of the tester program code.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: January 7, 2020
    Assignees: SAMSUNG ELECTRONICS CO., LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sung-Boem Park, Amir Nahir, Vitali Sokhin, Wisam Kadry, Jin Sung Park, Ara Cho
  • Patent number: 10387208
    Abstract: A method comprising, in a cloud computing system: receiving a new job at the cloud computing system; sampling VMs (Virtual Machines) of the cloud computing system for the load currently handled by each of the VMs; if the load currently handled by the VMs is within operational bounds, sending the new job to one of the VMs which currently handles the highest load compared to other ones of the VMs; and if the load currently handled by the VMs is beyond operational bounds, sending the new job to one of the VMs which currently handles the lowest load compared to other ones of the VMs.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: August 20, 2019
    Assignee: Technion Research & Development Foundation Limited
    Inventors: Amir Nahir, Ariel Orda, Dan Raz
  • Publication number: 20180212773
    Abstract: Systems, methods, and computer-readable storage media are provided for enabling discovery of a user by a member of an inner circle of the member when the user is in close proximity to the member. An indication is received from a user device indicating members of an inner circle of the user. A private key is sent to the mobile devices of each member of the inner circle. When the user device broadcasts an encrypted identifier, member devices with the private key can decrypt the encrypted identifier, allowing the member to discover that the user is in close proximity The user can also update membership of the inner circle so that only members presently in the inner circle can discover that the user is in close proximity.
    Type: Application
    Filed: January 25, 2017
    Publication date: July 26, 2018
    Inventors: Alona Kushnirsky, Haim Somech, Oded Nahir
  • Patent number: 9852037
    Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: James N. Klazynski, Amir Nahir
  • Patent number: 9823863
    Abstract: Data associated with logical addresses are received where the data is to be stored on a plurality of solid state storage dies and each of the plurality of solid state storage dies is independently accessible. Metadata is generated that includes the logical addresses where the metadata and the data sum to an amount of information that is less than a maximum amount of information that can be written to the plurality of solid state storage dies in a single write operation. The metadata and the data are stored in the plurality of solid state storage dies.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: November 21, 2017
    Assignee: SK Hynix Memory Solutions Inc.
    Inventors: Hong Lu, Nahir Sarmicanic, Suneel Kumar Indupuru
  • Patent number: 9804911
    Abstract: A method includes holding a definition of multiple software-implemented tests for testing one or more hardware units of an Integrated Circuit (IC), and of invocation conditions that specify whether the tests are permitted to run. The tests are applied to the hardware units at least partially in parallel, using a processor in the IC, by repeatedly tracking respective execution states of the tests and evaluating the invocation conditions, and invoking a test that currently does not run but is permitted to run in accordance with the invocation conditions.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: October 31, 2017
    Assignee: APPLE INC.
    Inventors: Amir Nahir, Randal S. Thelen, Yair Dagan, Yuval Gonczarowski
  • Publication number: 20170308866
    Abstract: Meeting scheduling resources are provided including systems and methods for optimizing proposed meeting details using historical information derived from meeting invitees. A statistical analysis, which may employ machine-learning techniques, may be used to determine a meeting attendance model based on past meetings and/or events, user activity, or other information associated with a user. Meeting patterns and availability for the user also may be used to generate the meeting attendance model. A meeting manager service may implement the meeting attendance models to facilitate schedule future meetings. The meeting manager service may also determine an attendance importance for invitees, a likelihood of attending the proposed meeting, given specific meeting features of the proposed meeting (such as time, location, or other meeting features) and recommend optimal meeting features for the proposed meeting.
    Type: Application
    Filed: April 22, 2016
    Publication date: October 26, 2017
    Inventors: Dikla Dotan-Cohen, Adi Miller, Haim Somech, Oded Nahir
  • Patent number: 9678151
    Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: James N. Klazynski, Amir Nahir
  • Patent number: 9626267
    Abstract: A method, apparatus and product for test generation. The method comprises generating a first set of instructions for a hardware component, that are to be executed when operating in a first mode of operation; in response to a parsed template statement being a marker statement, generating an intermediary set of one or more instructions to cause the hardware component to change the mode of operation to a second mode in accordance with the marker instruction, and modifying the expected mode of the hardware component to a second mode; and generating a second set of instructions for the hardware component, that are to be executed when operating in the second mode of operation. The generation of instructions comprises determining the expected mode and generating instructions in accordance with the expected mode of the hardware component. The generation is performed without having an expected full state of the hardware component.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Sung-Boem Park, Amir Nahir, Vitali Sokhin, Wisam Kadry, Jin Sung Park, Ara Cho
  • Patent number: 9626265
    Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: James N. Klazynski, Amir Nahir
  • Publication number: 20170103008
    Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.
    Type: Application
    Filed: December 22, 2016
    Publication date: April 13, 2017
    Inventors: James N. Klazynski, Amir Nahir
  • Patent number: 9569345
    Abstract: Localizing errors by: (i) running the testcase on a software model version of a processor to yield first testcase-run results in the form of a first set of values respectively stored in the set of data storage locations; (ii) creating a resource dependency information set based on the instructions of the testcase; (iii) running the testcase on a hardware version of the processor to yield second testcase-run results in the form of a second set of values respectively stored in the set of data storage locations; (iv) determining a set of miscompare data storage location(s), including at least a first miscompare data storage location, by comparing the first set of values and the second set of values; and (v) creating an initial dynamic slice of the data flow.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Ophir Friedler, Wisam Kadry, Amir Nahir, Vitali Sokhin
  • Publication number: 20160378626
    Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.
    Type: Application
    Filed: June 29, 2015
    Publication date: December 29, 2016
    Inventors: James N. Klazynski, Amir Nahir
  • Publication number: 20160378581
    Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.
    Type: Application
    Filed: February 2, 2016
    Publication date: December 29, 2016
    Inventors: James N. Klazynski, Amir Nahir
  • Publication number: 20160377680
    Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.
    Type: Application
    Filed: August 25, 2016
    Publication date: December 29, 2016
    Inventors: James N. Klazynski, Amir Nahir
  • Patent number: 9519756
    Abstract: Systems, methods, and computer-readable storage media are provided for managing policy and permissions profiles. Individuals or organizations are permitted to author profiles utilizing a profile template and publish such authored profiles for access and adoption by others. Users are able to import desired profiles and subsequently have those imported profiles applied each time he or she accesses an application or service to which the profile pertains. User interfaces from which users may view profiles associated with them, make alterations to settings of profiles associated with them, and/or select from a plurality of profiles for a particular application or service are also provided. Still further, recommendations may be provided to users for policy and permissions profiles based upon, for instance, crowd-sourcing, profiles adopted by social network connections of a user or other users that are “like” a user, prior profile selections made by the user, and/or prior user behavior.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 13, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Hadas Bitran, Marc E. Davis, Haim Somech, Ho John Lee, Allen G. Jones, Oded Nahir, Jeffrey D. Friedberg
  • Patent number: 9513985
    Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: James N. Klazynski, Amir Nahir
  • Publication number: 20160350163
    Abstract: A method includes holding a definition of multiple software-implemented tests for testing one or more hardware units of an Integrated Circuit (IC), and of invocation conditions that specify whether the tests are permitted to run. The tests are applied to the hardware units at least partially in parallel, using a processor in the IC, by repeatedly tracking respective execution states of the tests and evaluating the invocation conditions, and invoking a test that currently does not run but is permitted to run in accordance with the invocation conditions.
    Type: Application
    Filed: May 27, 2015
    Publication date: December 1, 2016
    Inventors: Amir Nahir, Randal S. Thelen, Yair Dagan, Yuval Gonczarowski
  • Publication number: 20160224448
    Abstract: A method, apparatus and product for test generation. The method comprises generating a first set of instructions for a hardware component, that are to be executed when operating in a first mode of operation; in response to a parsed template statement being a marker statement, generating an intermediary set of one or more instructions to cause the hardware component to change the mode of operation to a second mode in accordance with the marker instruction, and modifying the expected mode of the hardware component to a second mode; and generating a second set of instructions for the hardware component, that are to be executed when operating in the second mode of operation. The generation of instructions comprises determining the expected mode and generating instructions in accordance with the expected mode of the hardware component. The generation is performed without having an expected full state of the hardware component.
    Type: Application
    Filed: January 30, 2015
    Publication date: August 4, 2016
    Inventors: Sung-Boem Park, Amir Nahir, Vitali Sokhin, Wisam Kadry, Jin Sung Park, Ara Cho