Abstract: A preparation method, a product and an application of a composite membrane with a self-repairing function are provided by the present application, relating to the technical field of surface treatment of metallic materials. The preparation method includes the following steps: adding cobalt salt, tungsten salt, complexing agent and buffering agent into water to obtain a mixed solution, and adjusting a pH value to acidity to obtain an acidic solution; adding cerium oxide and surfactant into the acidic solution to obtain an electrolyte system; and placing a metal substrate in the electrolyte system for electrodeposition to obtain the composite membrane with self-repairing function. By means of constant potential composite electrodeposition on a metallic material substrate, the invention eventually forms a micron-scale composite membrane with a self-healing function and a thickness of 6-8 micrometers on the surfaces of the metallic materials.

Abstract: A micro LED display device includes an epitaxial structure layer, a connection layer, a light conversion layer and a transparent layer. The epitaxial structure layer includes a plurality of micro LEDs disposed apart from each other. The connection layer is disposed at one side of the epitaxial structure layer away from the micro LEDs. The light conversion layer is fixed on the epitaxial structure layer through the connection layer and includes a plurality of light conversion portions. Each of the light conversion portions corresponds to one of the micro LEDs. The transparent layer is disposed at one side of the light conversion layer away from the epitaxial structure layer. The ratio of the thickness of the transparent layer to the width of each light conversion portion is between 0.1 and 40. A manufacturing method of the micro LED display device is also provided.

Abstract: The present disclosure provides a semiconductor device package including a first device, a second device, and a spacer. The first device includes a substrate having a first dielectric constant. The second device includes a dielectric element, an antenna, and a reinforcing element. The dielectric element has a second dielectric constant less than the first dielectric constant. The antenna is at least partially within the dielectric element. The reinforcing element is disposed on the dielectric element, and the reinforcing element has a third dielectric constant greater than the first dielectric constant. The spacer is disposed between the first device and the second device and configured to define a distance between the first device and the second device.

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

Abstract: A semiconductor device includes a first wafer comprising a first portion of a seal ring structure within a body of the first wafer. The semiconductor device includes a second wafer comprising a second portion of the seal ring structure within a body of the second wafer. The second wafer is affixed to the first wafer such that the second portion of the seal ring structure is on the first portion of the seal ring structure. The semiconductor device includes a trench structure comprising a first trench in the first wafer and a second trench in the second wafer, where the first trench and the second trench are on a same side of the seal ring structure.

Abstract: A micro LED display panel is provided. The micro LED display panel includes a driving substrate and a plurality of bonding pads disposed on the driving substrate and spaced apart from each other. The micro LED display panel also includes a plurality of micro LED structures electrically connected to the bonding pads. Each micro LED structure includes at least one electrode disposed on the side of the micro LED structure facing the driving substrate. The electrode has a normal contact surface and a side contact surface. The normal contact surface faces the driving substrate, and the side contact surface is laterally connected to the corresponding bonding pad.

Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

Abstract: A memory array includes a first bit-line stack disposed over a substrate, a first spacer, a first data storage structure, and a word line. The first bit-line stack includes a first bit line disposed over the substrate; and a first hard mask layer partially covering a top surface of the first bit line. The first spacer is disposed on a lower sidewall of a first sidewall of the first bit line. The first hard mask layer and the first spacer expose a top corner of the first bit line. The first data storage structure covers the top corner of the first bit line. The word line covers a sidewall of the first data storage structure.

Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.

Abstract: An array substrate is provided. The array substrate includes a base substrate and a plurality of gate lines, a plurality of data lines, a common electrode layer and a plurality of pixel units arranged in an array disposed on the base substrate. Each of the pixel units includes a plurality of sub-pixel units defined by gate lines and data lines disposed to intersect each other laterally and vertically. The common electrode layer includes a plurality of common electrode blocks that double as self-capacitance electrodes, each of the common electrode blocks is connected with at least one wire, and the wires are in the middle of sub-pixel units of a same column.

Abstract: A method of manufacturing a transistor structure includes forming a plurality of trenches in a substrate, lining the plurality of trenches with a dielectric material, forming first and second substrate regions at opposite sides of the plurality of trenches, and filling the plurality of trenches with a conductive material. The plurality of trenches includes first and second trenches aligned between the first and second substrate regions, and filling the plurality of trenches with the conductive material includes the conductive material extending continuously between the first and second trenches.

Abstract: An image sensor includes an array of image pixels and black level correction (BLC) pixels. Each BLC pixel includes a BLC pixel photodetector, a BLC pixel sensing circuit, and a BLC pixel optics assembly configured to block light that impinges onto the BLC pixel photodetector. Each BLC pixel optics assembly may include a first portion of a layer stack including a vertically alternating sequence of first material layers having a first refractive index and second material layers having a second refractive index. Additionally or alternatively, each BLC pixel optics assembly may include a first portion of a layer stack including at least two metal layers, each having a respective wavelength sub-range having a greater reflectivity than another metal layer. Alternatively or additionally, each BLC pixel optics assembly may include an infrared blocking material layer that provides a higher absorption coefficient than color filter materials within image pixel optics assemblies.

Abstract: The present disclosure relates to an integrated chip including a substrate and a pixel. The pixel includes a photodetector. The photodetector is in the substrate. The integrated chip further includes a first inner trench isolation structure and an outer trench isolation structure that extend into the substrate. The first inner trench isolation structure laterally surrounds the photodetector in a first closed loop. The outer trench isolation structure laterally surrounds the first inner trench isolation structure along a boundary of the pixel in a second closed loop and is laterally separated from the first inner trench isolation structure. Further, the integrated chip includes a scattering structure that is defined, at least in part, by the first inner trench isolation structure and that is configured to increase an angle at which radiation impinges on the outer trench isolation structure.

Abstract: Discussed herein is device contact sizing in integrated circuit (IC) structures. In some embodiments, an IC structure may include: a first source/drain (S/D) contact in contact with a first S/D region, and a second S/D contact in contact with a second S/D region, wherein the first S/D region and the second S/D region have a same length, and the first S/D contact and the second S/D contact have different lengths.

Abstract: A SHP2 phosphatase allosteric inhibitor and a drug containing said inhibitor, the SHP2 phosphatase allosteric inhibitor having the structure shown in formula (I), and the use of an optical isomer compound of the SHP2 phosphatase allosteric inhibitor or a pharmaceutically acceptable salt thereof in the preparation of drugs for the treatment of tumor diseases.

Abstract: This application relates to the battery field, and specifically, to an electrode plate, an electrochemical device, and an apparatus. The electrode plate of this application includes a current collector and an electrode active material layer disposed on at least one surface of the current collector, where the current collector includes a support layer and a conductive layer disposed on at least one surface of the support layer, a single-sided thickness D2 of the conductive layer satisfies 30 nm?D2?3 ?m, the support layer is made of a polymer material or a polymer composite material, and a thickness D1 of the support layer satisfies 1 ?m?D1?30 ?m; and the electrode active material layer includes an electrode active material, a binder, and a conductive agent.

Abstract: The disclosure discloses a low-loss transmission line structure, which belongs to the field of radio frequency transmission lines and includes at least two metal layers stacked in a vertical manner. A dielectric layer is filled between the metal layers. The metal layers include a signal transmission strip in a middle portion. Ground strips are provided on both sides of the signal transmission strip. Through holes are evenly distributed on the dielectric layer, and the signal transmission strips on each of the metal layers are connected through the through holes to form a signal transmission line. The ground strips on each metal layer are connected through the through holes.

Abstract: The present disclosure discloses a method for reducing the fructan content in food made of rice and flour using microwave heating and belongs to the technical field of food processing. Fermented products made of rice and flour are prepared using microwave heating and fructan in the products can be effectively degraded. Compared with traditional steaming, the method can remarkably reduce the fructan content in the fermented food, effectively alleviate the bowel stress sensitivity to the fermented rice and flour food by patients with irritable bowel syndrome (IBS), meet the daily dietary requirements of special crowds, has the advantages of simple process, green processing and environmental protection, and is suitable for large-scale industrial production.