Abstract: The present invention discloses an apparatus and method for performing cyclic redundancy check (CRC) on partial protocol data units (PDUs). The disclosed apparatus is designed to off-load the CRC calculation for transmit or receive from a host computer. According to the disclosed method, when generating CRC for partial PDUs, for each such PDUs a decision is made to determine whether a CRC action is required, i.e., if CRC should be calculated, checked or placed in the outgoing byte stream. When partial CRC calculation is performed the intermediate value is saved into memory and later is used for calculating the CRC for a consecutive partial PDU. In accordance with a preferred embodiment of the invention, the need to re-calculate the CRC in a case of a re-transmit request is eliminated.

Abstract: The present invention discloses an apparatus and method for performing cyclic redundancy check (CRC) on partial protocol data units (PDUs). The disclosed apparatus is designed to off-load the CRC calculation for transmit or receive from a host computer. According to the disclosed method, when generating CRC for partial PDUs, for each such PDUs a decision is made to determine whether a CRC action is required, i.e., if CRC should be calculated, checked or placed in the outgoing byte stream. When partial CRC calculation is performed the intermediate value is saved into memory and later is used for calculating the CRC for a consecutive partial PDU. In accordance with a preferred embodiment of the invention, the need to re-calculate the CRC in a case of a re-transmit request is eliminated.

Abstract: A method for accelerating storage access in a network. The method comprises receiving a data record having a plurality of data segments. The data segments are stored in a local memory of a network controller (NC). A virtual write buffer (VWB) entry is assigned for the incoming data record in the NC local memory. The data segments of said data record are reassemble using the VWB. The data record is sent from the network controller directly to an I/O controller of a storage device.

Abstract: The present invention discloses an apparatus and method for performing cyclic redundancy check (CRC) on partial protocol data units (PDUs). The disclosed apparatus is designed to off-load the CRC calculation for transmit or receive from a host computer. According to the disclosed method, when generating CRC for partial PDUs, for each such PDUs a decision is made to determine whether a CRC action is required, i.e., if CRC should be calculated, checked or placed in the outgoing byte stream. When partial CRC calculation is performed the intermediate value is saved into memory and later is used for calculating the CRC for a consecutive partial PDU. In accordance with a preferred embodiment of the invention, the need to re-calculate the CRC in a case of a re-transmit request is eliminated.

Abstract: An apparatus and method are provided for scheduling transmit network events in a multiprocessing environment. Each processing node handles its own linked list of transmit object queues and linked list of transport queues. Therefore efficient handling of the transmit network events is enabled. Queues may be added, made inactive, or removed depending on the status of a specific transmit event the queue handles. By maintaining queues in memory, the apparatus is easily scalable, in linear relationship with the size of the memory made available.

Abstract: A memory system with folding error correction. The memory comprises a first memory bank and a second memory bank. A means for generating error correction code for data to be written to said memory system is provided. A means for writing said received data to a location in said first memory bank corresponding to a received address of said received data is provided. Further, a means for generating an error correction code write address in said second memory bank based on said received address. Still further, a means for writing said error correction code to said error correction code write address is provided.

Abstract: The present invention discloses an apparatus and method for performing cyclic redundancy check (CRC) on partial protocol data units (PDUs). The disclosed apparatus is designed to off-load the CRC calculation for transmit or receive from a host computer. According to the disclosed method, when generating CRC for partial PDUs, for each such PDUs a decision is made to determine whether a CRC action is required, i.e., if CRC should be calculated, checked or placed in the outgoing byte stream. When partial CRC calculation is performed the intermediate value is saved into memory and later is used for calculating the CRC for a consecutive partial PDU. In accordance with a preferred embodiment of the invention, the need to re-calculate the CRC in a case of a re-transmit request is eliminated.

Abstract: A method for accelerating storage access in a network. The method comprises receiving a data record having a plurality of data segments. The data segments are stored in a local memory of a network controller (NC). A virtual write buffer (VWB) entry is assigned for the incoming data record in the NC local memory. The data segments of said data record are reassemble using the VWB. The data record is sent from the network controller directly to an I/O controller of a storage device.

Abstract: An apparatus and method are provided for termination of received network events (i.e., a packet received from the network) in a multiprocessing environment. Each processing node may handle one or more receive object queues, which may be linked in a linked list fashion, as well as a linked list of application stream queues to enable efficient termination of the received network events. Queues may be added, made inactive, or removed, depending on the status of a specific receive event the queue handles. By maintaining queues in memory the apparatus is easily scalable, linearly with the size of the memory made available.

Abstract: An apparatus and method are provided for termination of received network events (i.e., a packet received from the network) in a multiprocessing environment. Each processing node may handle one or more receive object queues, which may be linked in a linked list fashion, as well as a linked list of application stream queues to enable efficient termination of the received network events. Queues may be added, made inactive, or removed, depending on the status of a specific receive event the queue handles. By maintaining queues in memory the apparatus is easily scalable, linearly with the size of the memory made available.

Abstract: An apparatus and method are provided for scheduling transmit network events in a multiprocessing environment. Each processing node handles its own linked list of transmit object queues and linked list of transport queues. Therefore efficient handling of the transmit network events is enabled. Queues may be added, made inactive, or removed depending on the status of a specific transmit event the queue handles. By maintaining queues in memory, the apparatus is easily scalable, in linear relationship with the size of the memory made available.

Abstract: A networked system comprising a host computer. A data streamer is connected to the host computer. The data streamer is capable of transferring data between the host and networked resources using a memory location without moving the data within the memory location. A communication link connects the data streamer and networked resources.

Abstract: When a search key is supplied to a content addressable memory (CAM), the CAM signals indicate which CAM entries have matched the key. These signals are provided to a weight array to select the entry of the highest priority. Each entry's priority is indicated by a weight in the weight array. The weight array processing is pipelined. In pipeline stage 0, the most significant bits (bits 0) of the weights are examined, and the highest priorities are selected based on the most significant bits. At pipeline stage 1, the next most significant bits (bits 1) are examined, and so on.

Abstract: A history buffer system (12) for allowing the recovery of executed instructions comprises main history buffer (14) for storing addresses of issued instructions and at least one subsidiary history buffer (16, 22) associated with a predetermined type of data, such as fixed or floating point data. The subsidiary history buffer (16, 22) has a plurality of entries (Y, Z), each entry for storing a pointer to a register (18, 26) and the data stored in the register. The main history buffer (14) is arranged to store control data (fxtag, fptag) which associates the entries in a subsidiary history buffer with the appropriate issued instructions of the same data type stored in the main history buffer. The main history buffer (14) may comprise a storage entry for each issued instruction, each storage entry having a field for storing the address of an issued instruction, and at least one tag field (fxtag, fptag) corresponding to the at least one subsidiary history buffer (16, 22) for storing the control data.