Patents by Inventor Orazio P. Forlenza
Orazio P. Forlenza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9274173Abstract: A method, system, and computer program product to test a semiconductor device are described. The system includes an input interface to receive a set of test patterns to test the semiconductor device and a user selection corresponding to a subset of the set of test patterns. The system also includes a processor to process the subset of the set of test patterns to output test data to the semiconductor device.Type: GrantFiled: September 30, 2014Date of Patent: March 1, 2016Assignee: International Business Machines CorporationInventors: Donato O. Forlenza, Orazio P. Forlenza, Michael P. Grace, Bryan J. Robbins
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Patent number: 9274172Abstract: A method, system, and computer program product to test a semiconductor device are described. The method includes receiving a set of test patterns for testing the semiconductor device and a user selecting a subset of the set of test patterns. The method also includes cataloging a content of pattern files associated with the subset of the set of test patterns to generate a catalog, and processing the catalog to output test data to the semiconductor device.Type: GrantFiled: October 17, 2013Date of Patent: March 1, 2016Assignee: International Business Machines CorporationInventors: Donato O. Forlenza, Orazio P. Forlenza, Michael P. Grace, Bryan J. Robbins
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Publication number: 20160033571Abstract: A method of performing root cause identification for a failure on an integrated circuit with a logic built-in self-test (LBIST) system and an LBIST system to perform root cause identification are described. The system includes one or more channel scan paths, each of the one or more macros associated with each of the one or more channel scan paths being executed during a test cycle, and a processor to initiate one or more of the test cycles via an LBIST controller, identify a failing test cycle among the one or more of the test cycles, identify a failing channel scan path among the one or more channel scan paths for the failing cycle, identify the one or more macros associated with the failing channel scan path, and iteratively check each of the one or more macros associated with the failing channel scan path to perform the root cause identification.Type: ApplicationFiled: September 30, 2014Publication date: February 4, 2016Inventors: Donato O. Forlenza, Orazio P. Forlenza, Bryan J. Robbins
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Publication number: 20160033570Abstract: A method of performing root cause identification for a failure on an integrated circuit with a logic built-in self-test (LBIST) system and an LBIST system to perform root cause identification are described. The method includes completing one or more cycles of test with the LBIST system, each of the one or more cycles implementing one or more macros associated with each of one or more channel scan paths. The method also includes identifying, using a processor, a failing cycle among the one or more cycles of test, identifying a failing channel scan path among the one or more channel scan paths associated with the failing cycle, and identifying the one or more macros associated with the failing channel scan path. The method further includes iteratively checking each of the one or more macros associated with the failing channel scan path to perform the root cause identification.Type: ApplicationFiled: July 30, 2014Publication date: February 4, 2016Inventors: Donato O. Forlenza, Orazio P. Forlenza, Bryan J. Robbins
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Patent number: 9244756Abstract: A method of performing root cause identification for a failure on an integrated circuit with a logic built-in self-test (LBIST) system and an LBIST system to perform root cause identification are described. The method includes completing one or more cycles of test with the LBIST system, each of the one or more cycles implementing one or more macros associated with each of one or more channel scan paths. The method also includes identifying, using a processor, a failing cycle among the one or more cycles of test, identifying a failing channel scan path among the one or more channel scan paths associated with the failing cycle, and identifying the one or more macros associated with the failing channel scan path. The method further includes iteratively checking each of the one or more macros associated with the failing channel scan path to perform the root cause identification.Type: GrantFiled: July 30, 2014Date of Patent: January 26, 2016Assignee: International Business Machines CorporationInventors: Donato O. Forlenza, Orazio P. Forlenza, Bryan J. Robbins
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Patent number: 9244757Abstract: A method of performing root cause identification for a failure on an integrated circuit with a logic built-in self-test (LBIST) system and an LBIST system to perform root cause identification are described. The system includes one or more channel scan paths, each of the one or more macros associated with each of the one or more channel scan paths being executed during a test cycle, and a processor to initiate one or more of the test cycles via an LBIST controller, identify a failing test cycle among the one or more of the test cycles, identify a failing channel scan path among the one or more channel scan paths for the failing cycle, identify the one or more macros associated with the failing channel scan path, and iteratively check each of the one or more macros associated with the failing channel scan path to perform the root cause identification.Type: GrantFiled: September 30, 2014Date of Patent: January 26, 2016Assignee: International Business Machines CorporationInventors: Donato O. Forlenza, Orazio P. Forlenza, Bryan J. Robbins
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Publication number: 20150113350Abstract: A method, system, and computer program product to test a semiconductor device are described. The system includes an input interface to receive a set of test patterns to test the semiconductor device and a user selection corresponding to a subset of the set of test patterns. The system also includes a processor to process the subset of the set of test patterns to output test data to the semiconductor device.Type: ApplicationFiled: September 30, 2014Publication date: April 23, 2015Inventors: Donato O. Forlenza, Orazio P. Forlenza, Michael P. Grace, Bryan J. Robbins
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Publication number: 20150113349Abstract: A method, system, and computer program product to test a semiconductor device are described. The method includes receiving a set of test patterns for testing the semiconductor device and a user selecting a subset of the set of test patterns. The method also includes cataloging a content of pattern files associated with the subset of the set of test patterns to generate a catalog, and processing the catalog to output test data to the semiconductor device.Type: ApplicationFiled: October 17, 2013Publication date: April 23, 2015Applicant: International Business Machines CorporationInventors: Donato O. Forlenza, Orazio P. Forlenza, Michael P. Grace, Bryan J. Robbins
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Patent number: 7934134Abstract: A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.Type: GrantFiled: June 5, 2008Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Donato O. Forlenza, Orazio P. Forlenza, Bryan J. Robbins, Phong T. Tran
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Patent number: 7930601Abstract: A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.Type: GrantFiled: February 22, 2008Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Joseph Eckelman, Donato O. Forlenza, Orazio P. Forlenza, William J. Hurley, Thomas J. Knips, Gary William Maier, Phong T. Tran
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Patent number: 7908532Abstract: This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.Type: GrantFiled: February 16, 2008Date of Patent: March 15, 2011Assignee: International Business Machines CorporationInventors: Joseph Eckelman, Donato O. Forlenza, Orazio P. Forlenza, Robert B. Gass, Phong T. Tran
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Publication number: 20090307548Abstract: A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.Type: ApplicationFiled: June 5, 2008Publication date: December 10, 2009Inventors: Donato O. Forlenza, Orazio P. Forlenza, Bryan J. Robbins, Phong T. Tran
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Publication number: 20090217112Abstract: A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.Type: ApplicationFiled: February 22, 2008Publication date: August 27, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph Eckelman, Donato O. Forlenza, Orazio P. Forlenza, William J. Hurley, Thomas J. Knips, Gary William Maier, Phong T. Tran
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Publication number: 20090210763Abstract: This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.Type: ApplicationFiled: February 16, 2008Publication date: August 20, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph Eckelman, Donato O. Forlenza, Orazio P. Forlenza, Robert B. Gass, Phong T. Tran
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Publication number: 20090210761Abstract: A method, apparatus and computer program product are provided for implementing AC scan diagnostic of delay and AC scan chain defects in an integrated circuit chip under test using Functional Architecture Verification Patterns (AVPs) for enabling rapidly localizing identified defects to a failing Shift Register Latch (SRL). An Architecture Verification Pattern (AVP) test pattern set is generated using a chip design input and simulation. AVP test vectors are applied for starting chip clocks and initiating testing, such as Logic Built-In-Self-Test (LBIST).Type: ApplicationFiled: February 15, 2008Publication date: August 20, 2009Inventors: Donato O. Forlenza, Orazio P. Forlenza, Phong T. Tran
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Patent number: 7395470Abstract: A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.Type: GrantFiled: June 9, 2005Date of Patent: July 1, 2008Assignee: International Business Machines CorporationInventors: Todd M. Burdine, Donato O. Forlenza, Orazio P. Forlenza, William J. Hurley, Phong T. Tran
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Patent number: 7392449Abstract: A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the scan chain, and if the scan chain is defective (for example, based on the unloaded logic values), then localizing a defect in the scan chain from the unloaded logic values by comparison thereof with the known locations of the latches of the scan chain loaded with the known logic value via the fuses. The scan chain may be predesigned with fuses spaced periodically across the chain every n latches to facilitate subsequent localization of a detected defect in the scan chain.Type: GrantFiled: December 14, 2007Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: Todd M. Burdine, Donato O. Forlenza, Orazio P. Forlenza, William J. Hurley, Phong T. Tran
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Patent number: 7234090Abstract: A method, apparatus and program product for testing at least one scan chain in an electronic chip in which the scan chain is formed by shift register latches arranged in the chain having a scan path with input pins and output pins. A flush test is executed for the scan chain under test and the flush test diagnostics for the flush test are recorded. A scan test is then executed for the scan chain under test and further test diagnostics are recorded in the event either or both the flush test or the scan test fails. The recorded flush test diagnostics and further test diagnostics are then analyzed to identify a call to one or more probable failed or failing shift register latches in the tested scan chain. The further scan chain diagnostics may include Disturb, Deterministic, ABIST, LBIST and Look-Ahead diagnostics. The tests may also be conducted for different voltage levels to determine the sensitivity of the scan chain being tested to differing voltage levels.Type: GrantFiled: September 2, 2004Date of Patent: June 19, 2007Assignee: International Business Machines CorporationInventors: Charles J. Blasi, Todd M. Burdine, Orazio P. Forlenza
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Patent number: 7117415Abstract: Methods and systems for reducing the volume of test data associated with built in self testing (BIST) test methodologies (e.g., logical BIST, array BIST, etc.) and pattern structures are provided. Embodiments of the present invention store a limited number of “dynamic” test parameters for each test sequence that have changed relative to a previous test sequence.Type: GrantFiled: January 15, 2004Date of Patent: October 3, 2006Assignee: International Business Machines CorporationInventors: Donato O. Forlenza, Orazio P. Forlenza, William J. Hurley, Bryan J. Robbins
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Patent number: 6308290Abstract: Look ahead testing process diagnoses broken or stuck-at scan chains to a failing shift register latch for improving the final manufacturing process and suggesting potentials for design change prior to manufacturing in order to improve yield levels. Post test data collection, analysis, and diagnosis can be eliminated.Type: GrantFiled: May 20, 1999Date of Patent: October 23, 2001Assignee: International Business Machines CorporationInventors: Orazio P. Forlenza, Mary P. Kusko, Franco Motika