Patents by Inventor Orazio Pasquale Forlenza
Orazio Pasquale Forlenza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11378623Abstract: A method includes executing a test against a first structure and a second structure of a built-in self-test circuit. Each of the first and second structures include a plurality of latches arranged as a plurality of stump chains. The method also includes unloading a first result of the test from the plurality of stump chains of the first structure and a second result of the test from the plurality of stump chains of the second structure. The method further includes determining that the plurality of stump chains of the first structure includes a faulty latch based on the first result not matching the second result.Type: GrantFiled: December 8, 2020Date of Patent: July 5, 2022Assignee: International Business Machines CorporationInventors: Steven Michael Douskey, Orazio Pasquale Forlenza, Mary P. Kusko, Franco Motika, Gerard Michael Salem
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Publication number: 20220178996Abstract: A method includes executing a test against a first structure and a second structure of a built-in self-test circuit. Each of the first and second structures include a plurality of latches arranged as a plurality of stump chains. The method also includes unloading a first result of the test from the plurality of stump chains of the first structure and a second result of the test from the plurality of stump chains of the second structure. The method further includes determining that the plurality of stump chains of the first structure includes a faulty latch based on the first result not matching the second result.Type: ApplicationFiled: December 8, 2020Publication date: June 9, 2022Inventors: Steven Michael DOUSKEY, Orazio Pasquale FORLENZA, Mary P. KUSKO, Franco MOTIKA, Gerard Michael SALEM
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Patent number: 8086924Abstract: A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.Type: GrantFiled: October 13, 2008Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Phong T Tran
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Patent number: 8065575Abstract: A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a passing operating region and each scan chain is unloaded. The ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a failing operating region for the device under test. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.Type: GrantFiled: October 13, 2008Date of Patent: November 22, 2011Assignee: International Business Machines CorporationInventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Phong T Tran
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Patent number: 7921346Abstract: A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.Type: GrantFiled: October 31, 2008Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Bryan J. Robbins, Phong T. Tran
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Publication number: 20100115337Abstract: A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.Type: ApplicationFiled: October 31, 2008Publication date: May 6, 2010Inventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Bryan J. Robbins, Phong T. Tran
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Publication number: 20100095177Abstract: A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.Type: ApplicationFiled: October 13, 2008Publication date: April 15, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Phong T. Tran
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Publication number: 20100095169Abstract: A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a passing operating region and each scan chain is unloaded. The ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a failing operating region for the device under test. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.Type: ApplicationFiled: October 13, 2008Publication date: April 15, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Phong T. Tran
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Patent number: 7475308Abstract: A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.Type: GrantFiled: April 11, 2008Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Adrian C. Anderson, Todd Michael Burdine, Donato Orazio Forlenza, Orazio Pasquale Forlenza, William James Hurley, Phong T. Tran
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Publication number: 20080189583Abstract: A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.Type: ApplicationFiled: April 11, 2008Publication date: August 7, 2008Applicant: International Business Machines CorporationInventors: Adrian C. Anderson, Todd Michael Burdine, Donato Orazio Forlenza, Orazio Pasquale Forlenza, William James Hurley, Phong T. Tran
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Patent number: 7395469Abstract: A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.Type: GrantFiled: April 8, 2004Date of Patent: July 1, 2008Assignee: International Business Machines CorporationInventors: Adrian C. Anderson, Todd Michael Burdine, Donato Orazio Forlenza, Orazio Pasquale Forlenza, William James Hurley, Phong T. Tran
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Patent number: 7225374Abstract: An apparatus, program product and method utilize an ABIST circuit provided on an integrated circuit device to assist in the identification and location of defects in a scan chain that is also provided on the integrated circuit device. In particular, a defect in a scan chain may be detected by applying a plurality of pattern sets to a scan chain coupled to an ABIST circuit, collecting scan out data generated as a result of the application of the plurality of pattern sets to the scan chain, and using the collected scan out data to identify a defective latch in the scan chain.Type: GrantFiled: December 4, 2003Date of Patent: May 29, 2007Assignee: International Business Machines CorporationInventors: Todd Michael Burdine, Donato Orazio Forlenza, Orazio Pasquale Forlenza, William James Hurley, Steven Michnowski, James Bernard Webb