Abstract: A network adapter includes a network interface, a bus interface, a hardware-implemented data-path and a programmable Data-Plane Accelerator (DPA). The network interface is to communicate with a network. The bus interface is to communicate with an external device over a peripheral bus. The hardware-implemented data-path includes a plurality of packet-processing engines to process data units exchanged between the network and the external device. The DPA is to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path.

Abstract: In one embodiment, an apparatus comprises a source system comprising a processing device coupled to memory. The processing device is configured to obtain an IO operation corresponding to an address of the source system. The IO operation comprises first user data. The processing device is further configured to store metadata associated with the IO operation in a first journal barrier of a replication journal of the source system and to close the first journal barrier. The processing device is further configured to determine that the first user data associated with the IO operation is missing from the first journal barrier and to obtain second user data from the address. The processing device is further configured to identify an interval from the first journal barrier to a second journal barrier and to provide the first journal barrier and the interval to a destination system.

Abstract: A computerized system operating in conjunction with computerized apparatus and with a fabric target service in data communication with the computerized apparatus, the system comprising functionality residing on the computerized apparatus, and functionality residing on the fabric target service, which, when operating in combination, enable the computerized apparatus to coordinate access to data.

Abstract: The disclosed technology controls a digital inking device by communicating electrostatic inking signals between the digital inking device and an ink-receiving computing device in an inking mode enabling the digital inking device to render digital ink in a display of the ink-receiving computing device via the electrostatic inking signals, detecting proximity of a peripheral communication device relative to the digital inking device, transitioning the digital inking device from the inking mode to a non-inking mode that terminates communication of the electrostatic inking signals between the digital inking device and the ink-receiving computing device, based at least in part on the detecting operation, and communicating electrostatic data signals in the non-inking mode between the digital inking device and the peripheral communication device in the non-inking mode, based at least in part on the transitioning to the non-inking mode.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a configuration of a sleep mode, the configuration indicating a coding scheme used for a wake-up signal (WUS). The UE may receive a WUS message, the WUS message being encoded with product coding, wherein a coding stage of the product coding comprises locally-decodable coding. The UE may receive a communication based at least in part on the WUS message. Numerous other aspects are described.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, an apparatus may receive a wake-up signal (WUS) indicating that the user equipment (UE) is to perform a wake-up from a sleep mode. The apparatus may determine a set of parameters for a reference sequence to be used in association with performing a synchronization after the wake-up. The apparatus may receive the reference sequence based at least in part on the set of parameters. Numerous other aspects are described.

Abstract: A system includes a bus interface and circuitry. The bus interface is configured to communicate with an external device over a peripheral bus. The circuitry is configured to support a plurality of widgets that perform primitive operations used in implementing peripheral-bus devices, to receive a user-defined configuration, which specifies a user-defined peripheral-bus device as a configuration of one or more of the widgets, and to implement the user-defined peripheral-bus device toward the external device over the peripheral bus, in accordance with the user-defined configuration.

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a memory controller circuit and a plurality of networks formed from a plurality of individual network component circuits. The memory controller includes a PIO message control circuit that is configured to receive PIO messages addressed to individual network component circuits and determine whether to send the PIO messages to the individual network component circuits based on determine whether previous PIO messages are pending for the individual network component circuits. The PIO message control circuit is configured to delay a first PIO message at the PIO message control circuit in response to determining that previous PIO message is pending for the addressee of the first PIO message.

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a memory controller circuit and a plurality of networks formed from a plurality of individual network component circuits. The memory controller includes a PIO message control circuit that is configured to receive PIO messages addressed to individual network component circuits and determine whether to send the PIO messages to the individual network component circuits based on determine whether previous PIO messages are pending for the individual network component circuits. The PIO message control circuit is configured to delay a first PIO message at the PIO message control circuit in response to determining that previous PIO message is pending for the addressee of the first PIO message.

Abstract: A debris collection assembly can be alternatively configured to form: (i) a chute or bag holder and/or (ii) a bag hauler that can be utilized with conventional bags. The debris collection assembly can be formed from at least one planar member that can be selectively folded or otherwise configured to form a chute apparatus that can serve as a guide for directing loose debris into a bag. The planar member of the debris collection assembly can be removed from the bag and selectively reconfigured to form a hauler for selectively transporting a bag and its contents of desired distances.

Abstract: For efficient high availability for a multi-node cluster using a processor device in a computing environment, using duplicate, standby host-bus adaptors (HBAs) for alternate nodes with respect to a node with the duplicate, standby HBAs using duplicate credentials of active HBAs of the node for shutting down the node, taking an active HBA of the node offline, and/or activating one of the alternate nodes. A failed node is shut down by an active one of the plurality of alternate nodes using a fence device, and all jobs of the failed node are taken over by the active node using a shared data structure including SCSI device assignments, SCSI reservations, and required host notifications.

Abstract: For efficient reclamation of pre-allocated direct memory access (DMA) memory in a computing environment, hot-add random access memory (RAM) is emulated for a general purpose use by reclamation of pre-allocated DMA memory reserved at boot time by notifying a non-kernel use device user that the non-kernel use device has a smaller window, stopping and remapping to the smaller window, and notifying a kernel that new memory has been added, wherein the new memory is a region left after the remap. The hot-add RAM is split into at least two continuous parts.

Abstract: Methods, systems, and computer program product embodiments for cataloging data in a backup storage environment, by a processor device, are provided. In a storage system using tape library data replication between an originating site and one or more backup sites, data catalog data is replicated between the originating site and the backup site such that replicated data moved from the originating site to the backup site is placed into a catalog duplicative of the originating site.

Abstract: For efficient high availability for a multi-node cluster using a processor device in a computing environment, using duplicate, standby host-bus adaptors (HBAs) for alternate nodes with respect to a node with the duplicate, standby HBAs using duplicate credentials of active HBAs of the node for shutting down the node, taking an active HBA of the node offline, and/or activating one of the alternate nodes. A failed node is shut down by an active one of the plurality of alternate nodes using a fence device, and all jobs of the failed node are taken over by the active node using a shared data structure including SCSI device assignments, SCSI reservations, and required host notifications.

Abstract: For efficient high availability for a multi-node cluster using a processor device in a computing environment, using duplicate, standby host-bus adaptors (HBAs) for alternate nodes with respect to a node with the duplicate, standby HBAs using duplicate credentials of active HBAs of the node for shutting down the node, taking an active HBA of the node offline, and/or activating one of the alternate nodes.

Abstract: Executing multiple concurrent transactions on the single database schema using a single concurrent transaction database infrastructure, wherein the single database schema is a single concurrent transactional relational database.

Abstract: For efficient reclamation of pre-allocated direct memory access (DMA) memory in a computing environment, hot-add random access memory (RAM) is emulated for a general purpose use by reclamation of pre-allocated DMA memory reserved at boot time by notifying a non-kernel use device user that the non-kernel use device has a smaller window, stopping and remapping to the smaller window, and notifying a kernel that new memory has been added, wherein the new memory is a region left after the remap. The hot-add RAM is split into at least two continuous parts.

Abstract: For efficient reclamation of pre-allocated direct memory access (DMA) memory in a computing environment, hot-add random access memory (RAM) is emulated for a general purpose use by reclamation of pre-allocated DMA memory reserved at boot time for responding to an emergency by notifying a non-kernel use device user that the non-kernel use device has a smaller window, stopping and remapping to the smaller window, and notifying a kernel that new memory has been added, wherein the new memory is a region left after the remap.

Abstract: Methods, systems, and computer program product embodiments for cataloging data in a backup storage environment, by a processor device, are provided. In a storage system using tape library data replication between an originating site and one or more backup sites, data catalog data is replicated between the originating site and the backup site such that replicated data moved from the originating site to the backup site is placed into a catalog duplicative of the originating site.

Abstract: Executing multiple concurrent transactions on the single database schema using a single concurrent transaction database infrastructure, wherein the single database schema is a single concurrent transactional relational database.