Patents by Inventor Oren Duer
Oren Duer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250156077Abstract: In various embodiments, a proxy application receives a first storage request from a proxy driver executing on a host node. The first storage request indicates a location within the shared storage system and a first address range associated with the host node. The proxy application converts the first storage request to a second storage request that indicates the location and a second address range associated with a proxy node. The proxy application transmits the second storage request to a storage driver that executes on the proxy node and is associated with the shared storage system. The storage driver invokes a remote direct memory access data transfer operation between the shared storage system and the host node to fulfill the first storage request.Type: ApplicationFiled: November 11, 2024Publication date: May 15, 2025Inventors: Chris J. NEWBURN, Eliav BAR-ILAN, Oren DUER, Max GURTOVOY, Kiran Kumar MODUKURI, Gal SHALOM, Roman SPIEGELMAN, Vishwanath VENKATESAN, Aviad YEHEZKEL, Yorey ZACK
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Patent number: 12248372Abstract: In one embodiment, a system includes a storage device controller including a first controller to read commands from a submission queue stored in a shared memory, provide the commands to a second controller, and write completion notices received from the second controller to a completion queue in the shared memory, and the second controller to receive the commands from the first controller, perform storage operations with a non-volatile memory responsively to receiving the commands, generate the completion notices responsively to performing the storage operations, provide the completion notices to the first controller, write recovery data about the commands and the completion notices to a persistent memory, and recover from a failure responsively to retrieving the recovery data from the persistent memory.Type: GrantFiled: March 19, 2023Date of Patent: March 11, 2025Assignee: Mellanox Technologies, Ltd.Inventors: Roman Spiegelman, Eliav Bar-Ilan, Oren Duer
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Patent number: 12248416Abstract: A network adapter includes a network interface, a bus interface, a hardware-implemented data-path and a programmable Data-Plane Accelerator (DPA). The network interface is to communicate with a network. The bus interface is to communicate with an external device over a peripheral bus. The hardware-implemented data-path includes a plurality of packet-processing engines to process data units exchanged between the network and the external device. The DPA is to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path.Type: GrantFiled: May 6, 2024Date of Patent: March 11, 2025Assignee: Mellanox Technologies, LtdInventors: Daniel Marcovitch, Eliav Bar-Ilan, Ran Avraham Koren, Liran Liss, Oren Duer, Shahaf Shuler
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Patent number: 12147716Abstract: Methods and systems provided herein involve extracting an input/output (I/O) operation from a packet received over an I/O pipeline, the I/O operation comprising either a read request to read data from at least one storage device or a write request to write data to the at least one storage device; determining that an address associated with the I/O operation exists in a lookup table that is provided for thin provisioning of the at least one storage device; performing one or more RAID calculations associated with the at least one storage device based on the address and the I/O operation; and accessing the at least one storage device to perform the I/O operation based on the one or more RAID calculations; and second processing component configured to carry out a second set of operations that occur when the address associated with the I/O operation does not exist in the lookup table.Type: GrantFiled: January 27, 2022Date of Patent: November 19, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Omri Kahalon, Gal Shalom, Aviad Yehezkel, Liran Liss, Oren Duer, Rabie Loulou, Maxim Gurtovoy
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Publication number: 20240311250Abstract: In one embodiment, a system includes a storage device controller including a first controller to read commands from a submission queue stored in a shared memory, provide the commands to a second controller, and write completion notices received from the second controller to a completion queue in the shared memory, and the second controller to receive the commands from the first controller, perform storage operations with a non-volatile memory responsively to receiving the commands, generate the completion notices responsively to performing the storage operations, provide the completion notices to the first controller, write recovery data about the commands and the completion notices to a persistent memory, and recover from a failure responsively to retrieving the recovery data from the persistent memory.Type: ApplicationFiled: March 19, 2023Publication date: September 19, 2024Inventors: Roman Spiegelman, Eliav Bar-Ilan, Oren Duer
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Publication number: 20240289288Abstract: A network adapter includes a network interface, a bus interface, a hardware-implemented data-path and a programmable Data-Plane Accelerator (DPA). The network interface is to communicate with a network. The bus interface is to communicate with an external device over a peripheral bus. The hardware-implemented data-path includes a plurality of packet-processing engines to process data units exchanged between the network and the external device. The DPA is to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path.Type: ApplicationFiled: May 6, 2024Publication date: August 29, 2024Inventors: Daniel Marcovitch, Eliav Bar-Ilan, Ran Avraham Koren, Liran Liss, Oren Duer, Shahaf Shuler
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Publication number: 20240272924Abstract: Systems and methods are presented that reduce the downtime of communication when updating backend software of an accelerated emulation system. In at least one embodiment, by first transferring the context of the running software to the updated software and rebuilding the context map for the communication and programming the context in the accelerated emulated device, downtime can be reduced by only enabling the new software and disabling the original software after the context map has been rebuilt as the last stage of execution.Type: ApplicationFiled: February 14, 2023Publication date: August 15, 2024Inventors: Parav Pandit, Oren Duer, Max Gurtovoy, Eliav Bar-Ilan, Shahaf Shuler
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Publication number: 20240231633Abstract: A system includes a hardware circuitry having a device coupled with one or more external memory devices. The device is to detect an input/output (I/O) request associated with an external memory device of the one or more external memory devices. The device is to record a first timestamp in response to detecting the I/O request transmitted to the external memory device. The device is further to detect an indication from the external memory device of a completion of the I/O request associated with the external memory device and record a second timestamp in response to detecting the indication. The device is also to determine a latency associated with the I/O request based on the first timestamp and the second timestamp.Type: ApplicationFiled: February 29, 2024Publication date: July 11, 2024Inventors: Shridhar Rasal, Oren Duer, Aviv Kfir, Liron Mula
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Patent number: 12007921Abstract: A network adapter includes a network interface, a bus interface, a hardware-implemented data-path and a programmable Data-Plane Accelerator (DPA). The network interface is to communicate with a network. The bus interface is to communicate with an external device over a peripheral bus. The hardware-implemented data-path includes a plurality of packet-processing engines to process data units exchanged between the network and the external device. The DPA is to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path.Type: GrantFiled: November 2, 2022Date of Patent: June 11, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Daniel Marcovitch, Eliav Bar-Ilan, Ran Avraham Koren, Liran Liss, Oren Duer, Shahaf Shuler
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Publication number: 20240143528Abstract: A network adapter includes a network interface, a bus interface, a hardware-implemented data-path and a programmable Data-Plane Accelerator (DPA). The network interface is to communicate with a network. The bus interface is to communicate with an external device over a peripheral bus. The hardware-implemented data-path includes a plurality of packet-processing engines to process data units exchanged between the network and the external device. The DPA is to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path.Type: ApplicationFiled: November 2, 2022Publication date: May 2, 2024Inventors: Daniel Marcovitch, Eliav Bar-Ilan, Ran Avraham Koren, Liran Liss, Oren Duer, Shahaf Shuler
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Patent number: 11947804Abstract: A system includes a hardware circuitry having a device coupled with one or more external memory devices. The device is to detect an input/output (I/O) request associated with an external memory device of the one or more external memory devices. The device is to record a first timestamp in response to detecting the IO request transmitted to the external memory device. The device is further to detect an indication from the external memory device of a completion of the IO request associated with the external memory device and record a second timestamp in response to detecting the indication. The device is also to determine a latency associated with the IO request based on the first timestamp and the second timestamp.Type: GrantFiled: April 6, 2022Date of Patent: April 2, 2024Assignee: NVIDIA CorporationInventors: Shridhar Rasal, Oren Duer, Aviv Kfir, Liron Mula
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Patent number: 11940935Abstract: A computerized system operating in conjunction with computerized apparatus and with a fabric target service in data communication with the computerized apparatus, the system comprising functionality residing on the computerized apparatus, and functionality residing on the fabric target service, which, when operating in combination, enable the computerized apparatus to coordinate access to data.Type: GrantFiled: April 19, 2021Date of Patent: March 26, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Eliav Bar-Ilan, Oren Duer, Maxim Gurtovoy, Liran Liss, Aviad Shaul Yehezkel
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Publication number: 20240095205Abstract: A system includes a bus interface and circuitry. The bus interface is configured to communicate with an external device over a peripheral bus. The circuitry is configured to support a plurality of widgets that perform primitive operations used in implementing peripheral-bus devices, to receive a user-defined configuration, which specifies a user-defined peripheral-bus device as a configuration of one or more of the widgets, and to implement the user-defined peripheral-bus device toward the external device over the peripheral bus, in accordance with the user-defined configuration.Type: ApplicationFiled: November 16, 2022Publication date: March 21, 2024Inventors: Daniel Marcovitch, Liran Liss, Aviad Shaul Yehezkel, Rabia Loulou, Oren Duer, Shahaf Shuler, Chenghuan Jia, Philip Browning Johnson, Gal Shalom, Omri Kahalon, Adi Merav Horowitz, Arpit Jain, Eliav Bar-Ilan, Prateek Srivastava
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Patent number: 11934658Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is to communicate with one or more hosts over a peripheral bus. The processing circuitry is to expose on the peripheral bus a peripheral-bus device that communicates with the one or more hosts using one or more instances of at least one bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the one or more hosts, and to complete the I/O transactions for the one or more hosts in accordance with one or more instances of at least one network storage protocol, by running at least part of a host-side protocol stack of the at least one network storage protocol.Type: GrantFiled: November 16, 2021Date of Patent: March 19, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Boris Pismenny, Oren Duer, Dror Goldenberg
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Patent number: 11934333Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is configured to communicate with a host over a peripheral bus. The processing circuitry is configured to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the host, and to complete the I/O transactions for the host in accordance with a network storage protocol, by running at least part of a host-side protocol stack of the network storage protocol.Type: GrantFiled: March 25, 2021Date of Patent: March 19, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Oren Duer, Dror Goldenberg
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Patent number: 11892964Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is configured to communicate with a host over a peripheral bus. The processing circuitry is configured to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the host, and to complete the I/O transactions for the host in accordance with a network storage protocol, by running at least part of a host-side protocol stack of the network storage protocol.Type: GrantFiled: March 25, 2021Date of Patent: February 6, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Oren Duer, Dror Goldenberg
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Publication number: 20230325089Abstract: A system includes a hardware circuitry having a device coupled with one or more external memory devices. The device is to detect an input/output (I/O) request associated with an external memory device of the one or more external memory devices. The device is to record a first timestamp in response to detecting the IO request transmitted to the external memory device. The device is further to detect an indication from the external memory device of a completion of the IO request associated with the external memory device and record a second timestamp in response to detecting the indication. The device is also to determine a latency associated with the IO request based on the first timestamp and the second timestamp.Type: ApplicationFiled: April 6, 2022Publication date: October 12, 2023Inventors: Shridhar Rasal, Oren Duer, Aviv Kfir, Liron Mula
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Publication number: 20230236769Abstract: Methods and systems provided herein involve extracting an input/output (I/O) operation from a packet received over an I/O pipeline, the I/O operation comprising either a read request to read data from at least one storage device or a write request to write data to the at least one storage device; determining that an address associated with the I/O operation exists in a lookup table that is provided for thin provisioning of the at least one storage device; performing one or more RAID calculations associated with the at least one storage device based on the address and the I/O operation; and accessing the at least one storage device to perform the I/O operation based on the one or more RAID calculations; and second processing component configured to carry out a second set of operations that occur when the address associated with the I/O operation does not exist in the lookup table.Type: ApplicationFiled: January 27, 2022Publication date: July 27, 2023Inventors: Omri Kahalon, Gal Shalom, Aviad Yehezkel, Liran Liss, Oren Duer, Rabie Loulou, Maxim Gurtovoy
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Patent number: 11693804Abstract: A computerized system for efficient interaction between a host, the host having a first operating system, and a second operating system, the system comprising a subsystem on the second operating system which extracts data, directly from a buffer which is local to the host, wherein the system is operative for mapping memory from one bus associated with the first operating system to a different bus, associated with the second operating system and from which different bus the memory is accessed, thereby to emulate a connection between the first and second operating systems by cross-bus memory mapping.Type: GrantFiled: June 3, 2021Date of Patent: July 4, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Alex Rosenbaum, Oren Duer, Alexander Mikheev, Nitzan Carmi, Haggai Eran
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Publication number: 20230104492Abstract: In one embodiment, a processing apparatus includes a processor to train an artificial intelligence model to find a pacing action from which to derive a pacing metric for use in serving content transfer requests.Type: ApplicationFiled: April 5, 2022Publication date: April 6, 2023Inventors: Gary Mataev, Shahaf Shuler, Amit Mandelbaum, Shridhar Rasal, Oren Duer, Benjamin Alexis Solomon Eli Fuhrer, Evgenii Kochetov, Gal Yefet