Abstract: A novel and useful system and method for leap second and daylight saving time (DST) correction for use in a radio controlled clock (RCC) receiver. The RCC receiver extracts schedule information from the frame, including the time for the DST transition and whether a leap second needs to be added at the end of this half-year. Linear error correcting coding is used for the leap second and the DST on/off indications, while non-linear error correcting coding (e.g., a look up table) is used for the DST schedule to enhance reception reliability in the presence of noise and interference. The one second/one hour corrections are scheduled to occur when they should take place and the correction is applied exactly when DST or leap second is to go into effect, without having to receive anything around the time of the correction.

Abstract: A novel and useful system and method for leap second and daylight saving time (DST) correction for use in a radio controlled clock (RCC) receiver. The RCC receiver extracts schedule information from the frame, including the time for the DST transition and whether a leap second needs to be added at the end of this half-year. Linear error correcting coding is used for the leap second and the DST on/off indications, while non-linear error correcting coding (e.g., a look up table) is used for the DST schedule to enhance reception reliability in the presence of noise and interference. The one second/one hour corrections are scheduled to occur when they should take place and the correction is applied exactly when DST or leap second is to go into effect, without having to receive anything around the time of the correction.

Abstract: A novel and useful system and method for leap second and daylight saving time (DST) correction for use in a radio controlled clock (RCC) receiver. The RCC receiver extracts schedule information from the frame, including the time for the DST transition and whether a leap second needs to be added at the end of this half-year. Linear error correcting coding is used for the leap second and the DST on/off indications, while non-linear error correcting coding (e.g., a look up table) is used for the DST schedule to enhance reception reliability in the presence of noise and interference. The one second/one hour corrections are scheduled to occur when they should take place and the correction is applied exactly when DST or leap second is to go into effect, without having to receive anything around the time of the correction.

Abstract: A novel and useful system and method for extracting timing, time and additional information from a broadcast received in a radio controlled clock (RCC) receiver. The RCC receiver extracts timing information represented by a known synchronization sequence that is used for acquisition and tracking purposes. The RCC receiver extracts time information as a merged 26-bit time information word linearly coded into 31 bits comprising the number of minutes (or hours) since the turn of the current century. A minute counter representing the 26 bits is converted into the date, hour, and minute. The RCC extracts additional information including the schedule for the next daylight saving time transition and for an imminent leap second. The communications protocol optionally employs error correcting codes to provide protection for data fields in the frame, which the RCC may use to enhance reception reliability in the presence of noise and interference.

Abstract: An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion calibration to compensate for nonlinearlities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital-to-frequency converter (DFC), DPA and PA. The on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, demodulates the RF PA output and uses the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. A sample of the RF output signal is provided to the receiver chain. While the PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.

Abstract: A novel and useful apparatus for and method of predistortion calibration and built-in self testing (BIST) of a nonlinear digitally-controlled radio frequency (RF) power amplifier (DPA) using subharmonic mixing. The RF power amplifier output is temporarily coupled into the frequency reference (FREF) input and the phase error samples generated in the phase locked loop (PLL) are then observed and analyzed. The digital predistortion and BIST mechanisms process the phase error samples to calibrate and test the DPA in the transmitter of the Digital RF Processor (DRP). The invention enables the characterization of nonlinearities, the configuration of internal predistortion, as well as the testing of the transmitter's analog/RF circuitry, thereby eliminating commonly employed RF performance testing using high-cost test equipment and associated extended test times.

Abstract: A novel and useful apparatus for and method of minimizing the phase distortions experienced at the output of a phase locked loop (PLL) by dithering of its input frequency reference to overcome additive interference that is parasitically suffered on it. The frequency reference signal is dithered in a controlled manner using either indirect or direct coupling. The dither signal may be a single clock or is generated by switching between two or more of the existing clock signals generated, or may be produced by a dedicated pseudo-random noise generator having specific spectral properties. In indirect coupling, the dither signal is coupled through a bond wire sufficiently close in proximity to the frequency reference circuit input. This dominates the jitter inflicted onto the frequency reference signal and upconverts its spectral content to higher frequency, thus eliminating the more damaging low-frequency jitter caused by the interfering RF signal.

Abstract: A system and method for a radio controlled clock receiver adapted to extract timing and time information from a phase modulated signal. The official time signal is broadcast from a central location using a modulation scheme that adds phase modulation to legacy pulse width modulated/amplitude modulation that allows for greatly improved performance. The information modulated onto the phase contains a known synchronization sequence having good autocorrelation properties, error-correcting coding for the time information and notifications of daylight-saving-time (DST) transitions that are provided months in advance. The modulation scheme is based on a form of phase modulation, such as binary-phase-shift-keying (BPSK) or phase reversal keying (PRK). A superframe comprising multiple frames with repeated information allows for the accumulation of received energy over multiple frames to provide for a corresponding gain in the receiver.

Abstract: A novel and useful adaptive frequency hopping scheme for wireless devices and networks operating in a congested environment of similar devices, where capacity maximization is desired. The hopping sequence of each wireless link is dynamically adapted such that the impact of the surrounding interference is minimized and the interference induced onto the coexisting systems is also minimized. The scheme detects the repetitive presence of interference on a particular channel and comprises a replacement mechanism for swapping the interfered frequency-channel with one that would be clear for that particular time-slot. The mechanism detects interference during a redundant portion of the transmission (i.e. header or trailer) without having to experience packet failures (i.e. data loss). If the interference impact (e.g.

Abstract: A mixed-signal integrator, having an analog input and a digital output, is adapted to perform an integration operation partially in the analog domain and partially in the digital domain while eliminating the limitations of a conventional analog integrator. The integrator also digitizes a signal of interest without the use of a conventional sampling operation followed by a conventional analog-to-digital converter. The analog integrator portion generates an analog integration signal limited between low and high rail voltages defined by two comparators with corresponding threshold voltages. When either rail voltage is reached, the polarity of the input signal is reversed to prevent the integration result from exceeding that rail. Each such event is also tracked in digital logic, which provides a count whenever two consecutive such events correspond to the two different rails. At the end of the integration duration this count serves as the digital representation of the integration result.

Abstract: A novel apparatus and method of linearization of a digitally controlled pre-power amplifier (DPA) and RF power amplifier (PA). The mechanism is operative to perform predistortion calibration to compensate for nonlinearities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital to frequency converter (DFC), DPA and PA. The mechanism of the invention takes advantage of the on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, to demodulate the RF PA output and use the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. Controlled RF coupling is used to provide a sample of the RF output signal that to the receiver chain. The contents of the predistortion LUT are typically updated during the PA power up or down ramp.

Abstract: A method of cancelling alien noise in coordinated DSL lines, a method of smoothing an alien noise covariance estimate, and a processor and modem for cancelling alien noise in coordinated DSL lines. In one embodiment, the method of cancelling alien noise includes: (1) estimating alien noise vectors for at least some training symbols, (2) arranging the alien noise vectors in a matrix dimensioned for a number of coordinated DSL lines, (3) orthonormally transforming the matrix into a lower-triangular matrix and (4) computing alien noise prediction filters from the lower-triangular matrix.

Abstract: A timekeeping device that tracks the time provided by a digital broadcast and the protocol of that broadcast, defined by its data frame structure and modulation scheme, are adapted to allow for superior performance of the timekeeping devices in terms of range of operation, immunity to interference, ability to operate with lower cost antennas due to enhanced link robustness, and reduced energy consumption. The timekeeping device operates with infrequent receptions of the broadcast by relying on independent self-compensation. This alleviates the need for frequent receptions to ensure timing accuracy while reducing energy consumption. The mean and variability of successive measurements of timing drift are evaluated and an estimated upper bound for the drift-estimation error is set.

Abstract: A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. A technique is presented to synthesize the controllers within a single-loop sigma delta modulator such that the noise transfer function can be chosen arbitrarily from a family of functions satisfying certain conditions. Using the novel modulator design technique, polar and Cartesian (i.e. quadrature) transmitter structures are supported. A transmitter employing polar transmit modulation is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands. Similarly, a transmitter employing Cartesian transmit modulation is presented that shapes the spectral emissions of a hybrid power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.

Abstract: A novel and useful system for providing high transmission power using a shared Bluetooth and Wireless Local Area Network (WLAN) front end module (FEM). A single power amplifier in the front end module is shared between the WLAN and Bluetooth radio cores, thus providing a high power transmission option (Bluetooth class 1) for the Bluetooth core. Interface circuitry in the FEM couple either the WLAN TX output or the Bluetooth TX output to the input of the power amplifier and couple the output of the power amplifier to the external antenna. In the receive direction, the interface circuitry steers the antenna input to the respective WLAN or Bluetooth receivers in accordance with one or more control signals. Alternatively, a switch in the WLAN/Bluetooth radio chip functions to switch the Bluetooth TX output to a conventional FEM, thereby allowing the FEM power amplifier to be shared between the WLAN and Bluetooth radio cores.

Abstract: A novel and useful adaptive frequency hopping scheme for wireless devices and networks operating in a congested environment of similar devices, where capacity maximization is desired. The hopping sequence of each wireless link is dynamically adapted such that the impact of the surrounding interference is minimized and the interference induced onto the coexisting systems is also minimized. The scheme detects the repetitive presence of interference on a particular channel and comprises a replacement mechanism for swapping the interfered frequency-channel with one that would be clear for that particular time-slot. The mechanism detects interference during a redundant portion of the transmission (i.e. header or trailer) without having to experience packet failures (i.e. data loss). If the interference impact (e.g.

Abstract: A novel apparatus and method for a hybrid Cartesian/polar digital QAM modulator. The hybrid technique of the present invention utilizes a combination of an all digital phase locked loop (ADPLL) that features a wideband frequency modulation capability and a digitally controlled power amplifier (DPA) that features interpolation between 90 degree spaced quadrature phases. This structure is capable of performing either a polar operation or a Cartesian operation and can dynamically switch between them depending on the instantaneous value of a metric measured by a thresholder/router. In this manner, the disadvantages of each modulation technique are avoided while the benefits of each are exploited.

Abstract: A novel apparatus and method of improving the power efficiency of a digital transmitter for non-constant-amplitude modulation schemes. The power efficiency improvement mechanism of the invention leverages the high efficiency of a switched-mode power supply (SMPS) that supplies the high DC current to the transmitter's power amplifier, while compensating for its limitations using predistortion. The predistortion may be achieved using any suitable technique such as digital signal processing, hardware techniques, etc. A switched mode power supply (i.e. switching regulator) is used to provide a slow form (i.e. reduced bandwidth) of envelope tracking (based on a narrower bandwidth distorted version of the envelope waveform) such that the switching regulator can use a lower switching rate corresponding to the lower bandwidth, thereby obtaining high efficiency in the switching regulator.

Abstract: A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

Abstract: A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, ?). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I+jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.