Abstract: A portable millimeter-wave wireless communications device relies on millimeter-wave spectrum for wireless communications. The millimeter-wave device may be a smart-phone, a laptop computer or a tablet computer. The millimeter-wave device may be a module that is added to an existing portable device such as a smart-phone, a laptop computer or a tablet computer to provide millimeter-wave communications capability. The module may be incorporated into a protective encapsulating case of such portable devices.

Abstract: A portable millimeter-wave wireless communications device relies on millimeter-wave spectrum for wireless communications. The millimeter-wave device may be a smart-phone, a laptop computer or a tablet computer. The millimeter-wave device may be a module that is added to an existing portable device such as a smart-phone, a laptop computer or a tablet computer to provide millimeter-wave communications capability. The module may be incorporated into a protective encapsulating case of such portable devices.

Abstract: A portable millimeter-wave wireless communications device relies on millimeter-wave spectrum for wireless communications. The millimeter-wave device may be a smart-phone, a laptop computer or a tablet computer. The millimeter-wave device may be a module that is added to an existing portable device such as a smart-phone, a laptop computer or a tablet computer to provide millimeter-wave communications capability. The module may be incorporated into a protective encapsulating case of such portable devices.

Abstract: A digital nonlinear adaptive mechanism for frequency offset compensation for use in a digital Frequency Shift Keying (FSK) receiver such as a Bluetooth GFSK receiver. The mechanism is intended to aid in the recovery of a frequency-modulated signal in the presence of an unknown additive frequency offset, which could be greater than the peak frequency deviation and which must be suppressed to enable proper data recovery in the receiver. The mechanism utilizes a demodulator to convert the frequency offset into a digitally represented DC level. This level is extracted by a non-linear estimator based on peak detectors and filters. Active suppression of the DC level is achieved by feed-forwarding the estimated value into a subtractor that removes it from the digital signal. A gear shift mechanism incorporated within the DC estimation block enables the dynamic control of the DC estimation process.

Abstract: A system-on-a-chip (SoC), a method of serving a Stratum-1 clock signal from an SoC and a device including the SoC. In one embodiment, the SoC includes: (1) a monolithic substrate, (2) a time code receiver clock source supported by the monolithic substrate and configured to receive a timing signal and generate a clock signal for the SoC and (3) at least one of a processor, memory and other SoC circuitry supported by the monolithic substrate and configured to receive the clock signal from the time code receiver clock source.

Abstract: An integrated circuit (IC), a method of operating the IC and devices incorporating the IC. In one embodiment, the IC includes: (1) a monolithic substrate and (2) a time code receiver supported by the monolithic substrate and configured to receive a timing signal and employ the timing signal to adjust a local oscillator of a real time clock (RTC).

Abstract: An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillators to perform sensitivity testing. The on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated.

Abstract: A digitally controlled mechanism for the minimization of the self-interference caused by an amplitude modulated signal generated within a polar transmitter to the oscillator circuit, where the carrier of that transmitter is created. A digitally controlled delay between the circuit where the signal is generated and the circuit where it is amplitude-modulated allows adjustment of the delay or phase-shift between the aggressing and victim signals. The optimal delay that is to be introduced in the path is determined, and a corresponding control word is generated to arrive at the selected delay/phase-shift.

Abstract: An on-chip reduced complexity modulation noise estimation mechanism for performing nonlinear signal processing to analyze modulation noise to determine whether a semiconductor device under test complies with the performance criteria set by specifications or a standard corresponding thereto. When used in a two-point transmitter modulation architecture, the mechanism relies on the fact that the noise statistics at the output of the transmitter can be determined by observing the phase error output of the phase detector within the phase locked loop. In the digital embodiment of the mechanism, the phase error signal is compared to a configurable threshold value to generate an exception event. If the number of exception events exceeds a configurable max_fail value after comparisons of a configurable number of phase error samples, the test fails. A pass/fail signal is output reflecting the result of the test.

Abstract: An apparatus for and method of extending the dynamic range of a RF communications receiver. The invention provides a mechanism for controlling the gain of both the LNA and down conversion mixer in the front end portion of an RF receiver. Both the LNA and the mixer are adapted to have both low and high gain modes of operation. The control mechanism typically comprises a two bit gain control that places both the LNA and mixer in one of four operating gain mode states. The selection of the most appropriate operating gain mode state, is preferably determined in accordance with various metrics such as the received levels of the desired signal, levels of interference signals, bit error rate and receiver RSSI.

Abstract: One embodiment of the invention includes a method for testing the performance of a Global System for Mobile Communications (GSM) transmitter. The output of the GSM transmitter is converted to a digital signal. A power spectrum is estimated for the GSM transmitter according to the digital signal via a modified periodogram algorithm. A phase trajectory of the digital signal is determined, and an ideal phase signal is determined from the determined phase trajectory. A phase trajectory error is calculated from the determined phase trajectory and the determined ideal phase signal. A tested device may be considered compliant if the abovementioned phase error and spectral mask meet specific defined criteria, and fails the test if either of these does not meet the predefined limits. The present invention is targeted at reducing the test time and test equipment traditionally associated with the implementation of these tests.

Abstract: An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillators to perform sensitivity testing. Tile on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated.

Abstract: An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillator, to perform sensitivity testing. The on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated.

Abstract: A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

Abstract: A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, ?). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I+jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.

Abstract: A digital demodulator employing a digital differential detection mechanism based on extracting phase differences directly from the I and Q signals after downconversion to zero-IF and image rejection are performed. The phase of the input I and Q signals is determined using the principle that the phase is equivalent to arctan ( Q I ) . A lookup table stores the values of the arctan function preferably in a reduced size format. The size of the lookup table can be reduced significantly by storing arctan values for the first quadrant only (i.e. 0 to 90°) and taking advantage of the fact that the phase values for the other three quadrants can be derived from those of the first with some correction applied depending on the signs of the I and Q input samples. Phase extraction logic is provided that is operative to map the phase into the entire 0 to 360° range of phase values (i.e. ?? to +? radians) based on the signs of the I and Q signals.

Abstract: System and method for interfacing with a digital computer using a multi-function device. A preferred embodiment comprises a multi-function device comprising a controller configured to process information and regulate operations of the multi-function device, a sensor coupled to the controller, the sensor configured to capture information in a movement of the multi-function device or a movement of an object applied to the multi-function device and to provide the information to the controller, wherein the information is used to determine movement information. The multi-function device further comprises a radio frequency circuit also coupled to the controller, the radio frequency circuit is configured to exchange information with other devices via a plurality of communications networks, wherein one of the other devices is a computer and the information shared is movement information from the multi-function device.

Abstract: A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. A technique is presented to synthesize the controllers within a single-loop sigma delta modulator such that the noise transfer function can be chosen arbitrarily from a family of functions satisfying certain conditions. Using the novel modulator design technique, polar and Cartesian (i.e. quadrature) transmitter structures are supported. A transmitter employing polar transmit modulation is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands. Similarly, a transmitter employing Cartesian transmit modulation is presented that shapes the spectral emissions of a hybrid power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.

Abstract: An on-chip test mechanism for transceiver power amplifier and oscillator frequency for use with the transmitter portion of an integrated RF transceiver. The RF output from the power amplifier in the transmitter is input to a built-in dedicated analog comparator having a configurable threshold. The threshold is adjusted to a predetermined level at which crossings start to occur at the comparator output. The comparator outputs pulses only if the power amplifier output is above a minimum configurable level. The comparator output is input to a frequency divider whose frequency output is tested by a low cost external tester to determine the actual RF frequency thereby confirming generation of the correct oscillator frequency and that the amplitude of the signal at the output of the power amplifier is sufficiently high for the configurable threshold level to be exceeded, thereby determining the compliance of the output power with its defined specifications.

Abstract: A novel apparatus and method for a hybrid Cartesian/polar digital QAM modulator. The hybrid technique of the present invention utilizes a combination of an all digital phase locked loop (ADPLL) that features a wideband frequency modulation capability and a digitally controlled power amplifier (DPA) that features interpolation between 90 degree spaced quadrature phases. This structure is capable of performing either a polar operation or a Cartesian operation and can dynamically switch between them depending on the instantaneous value of a metric measured by a thresholder/router. In this manner, the disadvantages of each modulation technique are avoided while the benefits of each are exploited.