Patents by Inventor Oren Matus

Oren Matus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260081707
    Abstract: A communication system includes a primary clock device having a precision clock and configured to transmit pulse signals at a constant rate. The communication system further includes a plurality of agent devices, each agent device comprising an internal timestamp control loop, a timestamp generator configured to update timestamps at an adjustable increment rate, and control logic configured to synchronize the agent device with the primary clock device using the internal timestamp control loop. The control logic enables each agent device to maintain synchronization with the primary clock device by adjusting the adjustable increment rate based on timing differences between estimated and actual signal reception times.
    Type: Application
    Filed: November 21, 2025
    Publication date: March 19, 2026
    Inventors: Yam Gellis, Oren Matus, Liron Mula, Natan Manevich, Hillel Chapman, Dotan David Levi
  • Patent number: 12556295
    Abstract: A device includes a receiver including a timestamp generator to update timestamps at a first rate. The receiver is to estimate a first time for receiving a signal, wherein the signal is associated with a synchronization operation. The receiver is further to receive the signal at a second time. The receiver is further to determine a difference between the second time and the first time, wherein the difference is associated with an error of the timestamp generator of the receiver. The receiver can also adjust the first rate to a second rate at which to update the timestamps by the timestamp generator, responsive to determining the difference between the first time and the second time.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: February 17, 2026
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Yam Gellis, Oren Matus, Liron Mula, Natan Manevich, Hillel Chapman, Dotan David Levi
  • Publication number: 20250240110
    Abstract: In one embodiments, a first device includes a first n-pulse-per-second (nPPS) output interface to be connected to a second nPPS input interface of a second device via a first clock connection, and to send a first pulse at time A to the second nPPS input interface for receipt at time B, and a first nPPS input interface to be connected to a second nPPS output interface of the second device via a second clock connection, to receive a second pulse at time D from the second nPPS output interface sent at time C, and to log time D in a first memory, and delay computation circuitry to compute a clock connection delay in the first clock connection and/or the second clock connection based on time A, time D, and a time difference between receiving the first pulse in, and sending the second pulse from, the second device.
    Type: Application
    Filed: January 21, 2024
    Publication date: July 24, 2025
    Inventors: Natan Manevich, Dotan David Levi, Bar Shapira, Wojciech Wasko, Maciej Machnikowski, Oren Matus, Yam Gellis
  • Publication number: 20250047402
    Abstract: A device includes a receiver including a timestamp generator to update timestamps at a first rate. The receiver is to estimate a first time for receiving a signal, wherein the signal is associated with a synchronization operation. The receiver is further to receive the signal at a second time. The receiver is further to determine a difference between the second time and the first time, wherein the difference is associated with an error of the timestamp generator of the receiver. The receiver can also adjust the first rate to a second rate at which to update the timestamps by the timestamp generator, responsive to determining the difference between the first time and the second time.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 6, 2025
    Inventors: Yam Gellis, Oren Matus, Liron Mula, Natan Manevich, Hillel Chapman, Dotan David Levi
  • Patent number: 11070304
    Abstract: In one embodiment, a computer apparatus includes a first NIC including at least one network interface port to transfer data with a first packet-data network (PDN) including a master clock to provide a clock synchronization signal S1, a first physical hardware clock (PHC) to maintain a time value T1 responsively to S1, and a first clock controller to generate a clock synchronization signal S2 responsively to S1, S2 having a frequency set responsively to S1, and send S2 over a connection to a second NIC including at least one network interface port to transfer data with a second PDN, a second PHC, and a second clock controller to receive S2, update the second PHC with a time value T2 responsively to S2, send another clock synchronization signal to network nodes in the second PDN responsively to T2, the second NIC acting as a master clock in the second PDN.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: July 20, 2021
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dotan David Levi, Liron Mula, Avraham Ganor, Avi Urman, Aviad Raveh, Yuval Itkin, Oren Matus