Abstract: A reticle management system is disclosed that provides data storage and retrieval of data associated with each reticle, reticle carrier, and certain system attributes and also for the efficient movement and storage of reticles and reticle carriers. The reticle management system includes a reticle management controller, a central reticle database, and one or more reticle stockers that include a stocker controller, a stocker database, and a stocker unit. The reticle management controller is coupled to the central reticle database and each of the stocker controllers. Each stocker controller collects data on the reticles, reticle carriers, or both, that are stored within the associated stocker unit and stores this data in the stocker database. The reticle management controller retrieves the data in each stocker database via the associated stocker controller and stores this data in central reticle database.

Abstract: A reticle management system is disclosed that provides data storage and retrieval of data associated with each reticle, reticle carrier, and certain system attributes and also for the efficient movement and storage of reticles and reticle carriers. The reticle management system includes a reticle management controller, a central reticle database, and one or more reticle stockers that include a stocker controller, a stocker database, and a stocker unit. The reticle management controller is coupled to the central reticle database and each of the stocker controllers. Each stocker controller collects data on the reticles, reticle carriers, or both, that are stored within the associated stocker unit and stores this data in the stocker database. The reticle management controller retrieves the data in each stocker database via the associated stocker controller and stores this data in central reticle database.

Abstract: A system and method for limiting the number of simultaneously switching outputs of an integrated circuit chip to at or below a predetermined limit for the chip during a short, predetermined time window by dynamically arbitrating request signals from discrete on-chip logic elements for assignment of output pins according to the priority of the request signals based on the type and intended use of output signals from such elements, and the immediate state of the integrated circuit chip.