Patents by Inventor Oreste Madia
Oreste Madia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096711Abstract: A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate, depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, removing the first work function metal over the PMOS gate dielectric, and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. Semiconductor device structures including desired metal gate electrodes deposited by the methods of the disclosure are also disclosed.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Qi Xie, Chiyu Zhu, Kiran Shrestha, Pauline Calka, Oreste Madia, Jan Willem Maes, Michael Eugene Givens
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Publication number: 20240079495Abstract: A memory device includes a gate structure, a ferroelectric structure over and electrically connected with the gate structure, a channel structure over the ferroelectric structure, and a plurality of contact structures over the channel structure. The gate structure includes a first gate as a back gate, a second gate as a floating gate, and a tunneling layer sandwiched there-between. The plurality of contact structures is laterally spaced apart with each other by a predetermined distance. In some embodiments, the sidewalls of the first gate are aligned with sidewalls of the plurality of contact structures.Type: ApplicationFiled: January 10, 2023Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Marcus Johannes Henricus Van Dal, Georgios Vellianitis, Gerben DOORNBOS, Oreste Madia
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Publication number: 20240074315Abstract: A semiconductor structure includes a substrate, a device, a conductor, a backside interconnect, and a thermoelectric generator. The substrate has a front surface and a rear surface opposite to the front surface. The device is disposed on the front surface of the substrate. The conductor is disposed at or near the front surface of the substrate and electrically coupled to the device. The backside interconnect is disposed on the rear surface of the substrate and electrically coupled to the device. The thermoelectric generator is disposed in the substrate and electrically coupled to the device, and includes a first-type through via and a second-type through via. The first-type through via penetrates from the rear surface of the substrate to the conductor, and is connected to a first conductive feature of the backside interconnect and the conductor.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Oreste Madia, Gerben DOORNBOS
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Publication number: 20230411163Abstract: A method includes forming first sacrificial layers and first channel layers alternately stacked over a substrate; forming second channel layers and second sacrificial layers alternately stacked over the first sacrificial layers and the first channel layers, in which the second channel layers are made of a first semiconductive oxide; performing an etching process to remove portions of the first sacrificial layers and the second sacrificial layers; forming a gate structure in contact with the first channel layers and the second channel layers; forming first source/drain contacts on opposite sides of the gate structure and electrically connected to the first channel layers; and forming second source/drain contacts on the opposite sides of the gate structure and electrically connected to the second channel layers.Type: ApplicationFiled: June 16, 2022Publication date: December 21, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Georgios VELLIANITIS, Oreste MADIA, Gerben DOORNBOS, Marcus Johannes Henricus VAN DAL
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Publication number: 20230411482Abstract: A method includes forming a first dielectric layer over a substrate; forming a first transistor over a first side of the first dielectric layer; removing the substrate to expose a second side of the first dielectric layer opposite to the first side of the second dielectric layer; and forming a second transistor over the second side of the first dielectric layer. Forming the first transistor includes forming a semiconductor layer over the first side of the first dielectric layer; forming a first gate structure over the semiconductor layer; and forming source/drain epitaxy structures on opposite sides of the first gate structure. Forming the second transistor includes forming a semiconductive oxide layer over the second side of the first dielectric layer; forming a second gate structure over the semiconductive oxide layer; and forming source/drain contacts over the semiconductive oxide layer and on opposite sides of the second gate structure.Type: ApplicationFiled: June 17, 2022Publication date: December 21, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Oreste MADIA, Georgios VELLIANITIS, Gerben DOORNBOS, Marcus Johannes Henricus VAN DAL
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Publication number: 20230387296Abstract: A device and methods of forming the same are described. The device includes a substrate, source/drain regions disposed over the substrate, a ferroelectric layer disposed over the substrate, a gate electrode in contact with the ferroelectric layer, a first conductive contact disposed at a first end of the gate electrode, and a second conductive contact disposed at a second end opposite the first end of the gate electrode. The first and second conductive contacts are configured to allow a current to flow from the first conductive contact through the gate electrode to the second conductive contact.Type: ApplicationFiled: May 29, 2022Publication date: November 30, 2023Inventors: Gerben Doornbos, Oreste Madia, Georgios Vellianitis, Marcus Johannes Henricus Van Dal
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Publication number: 20230352296Abstract: A device structure and a formation method are provided. The method includes forming a first carbon-containing layer over a substrate and forming a hafnium-containing oxide layer over the first carbon-containing layer. The method also includes forming a second carbon-containing layer over the hafnium-containing oxide layer. The method further includes crystallizing the hafnium-containing oxide layer while the hafnium-containing oxide layer is between the first carbon-containing layer and the second carbon-containing layer.Type: ApplicationFiled: April 29, 2022Publication date: November 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Oreste MADIA, Georgios VELLIANITIS
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Patent number: 11776807Abstract: Methods for controlling the formation of oxygen containing thin films, such as silicon oxycarbide (SiOC) and silicon oxycarbonitride (SiOCN) thin films, on a substrate in a reaction space are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor that comprises oxygen and a second reactant that does not include oxygen. In some embodiments the plasma power can be selected from a range to achieve a desired step coverage or wet etch rate ratio (WERR) for films deposited on three dimensional features.Type: GrantFiled: October 22, 2021Date of Patent: October 3, 2023Assignee: ASM IP Holding, B.V.Inventors: Lingyun Jia, Viljami J. Pore, Marko Tuominen, Sun Ja Kim, Oreste Madia
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Publication number: 20230261060Abstract: A field effect transistor may include an active layer containing an oxide compound material of at least two atomic elements including a first element of tin and a second element selected from Ge, Si, P, S, F, Ti, Cs, and Na and located over a substrate. The field effect transistor may further include a gate dielectric located on the active layer, a gate electrode located on the gate dielectric, and a source contact structure and a drain contact structure contacting a respective portion of the active layer. The oxide compound material may include at least germanium and tin. The oxide compound semiconductor material may be used as a p-type semiconductor material in BEOL structures.Type: ApplicationFiled: May 9, 2022Publication date: August 17, 2023Inventors: Georgios Vellianitis, Oreste Madia, Gerben Doornbos, Marcus Johannes Henricus Van Dal
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Publication number: 20230260782Abstract: Methods for selectively depositing silicon oxycarbide (SiOC) thin films on a dielectric surface of a substrate relative to a metal surface without generating significant overhangs of SiOC on the metal surface are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor, a first Ar and H2 plasma, a second Ar plasma and an etchant.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Inventors: Jan Willem Maes, David Kurt de Roest, Oreste Madia
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Patent number: 11728164Abstract: Methods for selectively depositing oxide thin films on a dielectric surface of a substrate relative to a metal surface are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a first precursor comprising oxygen and a species to be included in the oxide, such as a metal or silicon, and a second plasma reactant. In some embodiments the second plasma reactant comprises a plasma formed in a reactant gas that does not comprise oxygen. In some embodiments the second plasma reactant comprises plasma generated in a gas comprising hydrogen.Type: GrantFiled: October 11, 2021Date of Patent: August 15, 2023Assignee: ASM IP HOLDING B.V.Inventors: Eva Tois, Viljami Pore, Suvi Haukka, Toshiya Suzuki, Lingyun Jia, Sun Ja Kim, Oreste Madia
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Patent number: 11664222Abstract: Methods of forming indium gallium zinc oxide (IGZO) films by vapor deposition are provided. The IGZO films may, for example, serve as a channel layer in a transistor device. In some embodiments atomic layer deposition processes for depositing IGZO films comprise an IGZO deposition cycle comprising alternately and sequentially contacting a substrate in a reaction space with a vapor phase indium precursor, a vapor phase gallium precursor, a vapor phase zinc precursor and an oxygen reactant. In some embodiments the ALD deposition cycle additionally comprises contacting the substrate with an additional reactant comprising one or more of NH3, N2O, NO2 and H2O2.Type: GrantFiled: October 16, 2020Date of Patent: May 30, 2023Assignee: ASM IP Holding, B.V.Inventors: Oreste Madia, Andrea Illiberi, Michael Eugene Givens, Tatiana Ivanova, Charles Dezelah, Varun Sharma
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Patent number: 11664219Abstract: Methods for selectively depositing silicon oxycarbide (SiOC) thin films on a dielectric surface of a substrate relative to a metal surface without generating significant overhangs of SiOC on the metal surface are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor, a first Ar and H2 plasma, a second Ar plasma and an etchant.Type: GrantFiled: September 1, 2021Date of Patent: May 30, 2023Assignee: ASM IP HOLDING B.V.Inventors: Jan Willem Maes, David Kurt de Roest, Oreste Madia
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Publication number: 20230047356Abstract: A semiconductor device is provided. The semiconductor device includes a gate layer, a semiconductor layer and a ferroelectric layer disposed between the gate layer and the semiconductor layer. The semiconductor layer includes a first material containing a Group III element, a rare-earth element and a Group VI element, the ferroelectric layer includes a second material containing a Group III element, a rare-earth element and a Group V element and the gate layer includes a third material containing a Group III element and a rare-earth element. A method of fabricating a semiconductor device is also provided.Type: ApplicationFiled: August 13, 2021Publication date: February 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Oreste Madia, Georgios Vellianitis, Gerben Doornbos, Marcus Johannes Henricus Van Dal
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Publication number: 20230041622Abstract: A ferroelectric memory device includes a substrate, a gate electrode, a ferroelectric layer, and a pair of source/drain electrodes. The gate electrode is disposed over the substrate. The ferroelectric layer at least covers two adjacent side surfaces of the gate electrode. The pair of source/drain electrodes is over the substrate and disposed on two opposite sides of the gate electrode respectively.Type: ApplicationFiled: February 11, 2022Publication date: February 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Oreste Madia, Georgios Vellianitis, Gerben Doornbos, Marcus Johannes Henricus Van Dal
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Publication number: 20230035216Abstract: A network computation device includes a stack of a plurality of arrays of magnetic tunnel junctions that are spaced apart along a stack direction, and at least one filament-forming dielectric material layer located between each vertically neighboring pair of arrays of magnetic tunnel junctions selected from the plurality of magnetic tunnel junctions.Type: ApplicationFiled: January 6, 2022Publication date: February 2, 2023Inventor: Oreste MADIA
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Publication number: 20230029647Abstract: A method of forming a semiconductor device may include depositing a NiAl layer on a substrate, oxidizing the NiAl layer to form a bilayer including a NiO semiconducting material layer and an AlOx layer on the NiO semiconducting material layer, forming a semiconductor layer including the NiO semiconducting material layer, the semiconductor layer also including a channel region, and forming a gate dielectric on the channel region of the semiconductor layer.Type: ApplicationFiled: January 19, 2022Publication date: February 2, 2023Inventor: Oreste MADIA
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Patent number: 11501965Abstract: Methods for depositing oxide thin films, such as metal oxide, metal silicates, silicon oxycarbide (SiOC) and silicon oxycarbonitride (SiOCN) thin films, on a substrate in a reaction space are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a first reactant that comprises oxygen and a component of the oxide, and a second reactant comprising reactive species that does not include oxygen species. In some embodiments the plasma power used to generate the reactive species can be selected from a range to achieve a desired step coverage or wet etch rate ratio (WERR) for films deposited on three dimensional features. In some embodiments oxide thin films are selectively deposited on a first surface of a substrate relative to a second surface, such as on a dielectric surface relative to a metal or metallic surface.Type: GrantFiled: May 4, 2018Date of Patent: November 15, 2022Assignee: ASM IP HOLDING B.V.Inventors: Lingyun Jia, Viljami J. Pore, Marko Tuominen, Sun Ja Kim, Oreste Madia, Eva Tois, Suvi Haukka, Toshiya Suzuki
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Publication number: 20220123131Abstract: Methods and systems for depositing threshold voltage shifting layers onto a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a threshold voltage shifting layer onto a surface of the substrate. The threshold voltage shifting layers are particularly useful for metal oxide semiconductor field effect transistors.Type: ApplicationFiled: October 13, 2021Publication date: April 21, 2022Inventors: Oreste Madia, Giuseppe Alessio Verni, Qi Xie, Michael Eugene Givens, Varun Sharma, Andrea Illiberi
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Publication number: 20220076949Abstract: Methods for selectively depositing oxide thin films on a dielectric surface of a substrate relative to a metal surface are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a first precursor comprising oxygen and a species to be included in the oxide, such as a metal or silicon, and a second plasma reactant. In some embodiments the second plasma reactant comprises a plasma formed in a reactant gas that does not comprise oxygen. In some embodiments the second plasma reactant comprises plasma generated in a gas comprising hydrogen.Type: ApplicationFiled: October 11, 2021Publication date: March 10, 2022Inventors: Eva Tois, Viljami Pore, Suvi Haukka, Toshiya Suzuki, Lingyun Jia, Sun Ja Kim, Oreste Madia