Patents by Inventor Orestis Polychroniou

Orestis Polychroniou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11308093
    Abstract: A method includes encoding, by an encoding engine, consecutive sections of a received data stream that includes a stream of values. The encoding includes identifying a minimum value in a section of the stream. The encoding includes determining, for each value in the section of the stream, respective differences with the minimum value. An encoded version of the section includes the minimum value and a mask value. The mask value is combined with respective portions of the respective differences to generate the respective differences of each value in the section. The encoded version of the section further includes the respective portions of the respective differences.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: April 19, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Orestis Polychroniou, Naresh Chainani, Ippokratis Pandis
  • Patent number: 10884939
    Abstract: A computer system comprises memory to store computer-executable instructions. The computer system may, as a result of execution of the instructions by one or more processors, cause the system to load a first subset of a set of data elements into a first cache, load a second subset of the set of data elements into a second cache, and as a result of elements of the first subset being processed, issue commands to place elements of the second subset into the first cache to enable processing the second subset to be processed from the first cache.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: January 5, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Orestis Polychroniou, Naresh Kishin Chainani, Ippokratis Pandis
  • Publication number: 20190377683
    Abstract: A computer system comprises memory to store computer-executable instructions. The computer system may, as a result of execution of the instructions by one or more processors, cause the system to load a first subset of a set of data elements into a first cache, load a second subset of the set of data elements into a second cache, and as a result of elements of the first subset being processed, issue commands to place elements of the second subset into the first cache to enable processing the second subset to be processed from the first cache.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 12, 2019
    Inventors: Orestis Polychroniou, Naresh Kishin Chainani, Ippokratis Pandis