Abstract: Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.

Abstract: Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.

Abstract: A trace network for debugging integrated circuits is disclosed. At least one functional network includes a plurality of components interconnected by a number of network switches, implemented on at least one integrated circuit. A trace network is also implemented on the at least one integrated circuit, and includes a plurality of trace circuits configured to generate trace data based on transactions between ones of the plurality of components. The plurality of trace circuits are coupled to one another by a plurality of trace network switches. The trace circuits are configured to convey the generated trace data to an interface, via the trace network, without using the at least one functional network.

Abstract: Systems, apparatuses, and methods for implementing a multi-die clock stop trigger are described. A computing system includes a plurality of semiconductor dies connected together and sharing a global clock stop trigger signal which is pulled high via a resistor tied to a supply voltage. Each semiconductor die has a clock generation unit which generates local clocks for the die. Each clock generation unit monitors for local clock stop triggers, and if one of the local triggers is detected, the clock generation unit stops local clocks on the die and pulls the global clock stop trigger signal low. When the other clock generation units on the other semiconductor dies detect the global clock stop trigger at the logic low level, these clock generation units also stop their local clocks. Captured data is then retrieved from the computing system for further analysis.

Abstract: An apparatus includes a register memory and circuitry. The register memory is configured to hold a minimal value specified for a performance measure of a given type of memory access commands, whose actual performance measures vary among memory devices. The circuitry is configured to receive a memory access command of the given type, to execute the received memory access command in one or more memory devices, and to acknowledge the memory access command not before reaching the minimal value stored in the register memory.

Abstract: An apparatus for use with a memory device that has a plurality of memory-device terminals having respective unique bit significances is described. The apparatus includes a memory controller, which includes (i) a plurality of external terminals, each one of the external terminals configured to be in communication with a respective one of the memory-device terminals, (ii) a plurality of internal terminals having respective unique bit significances, (iii) a switching unit, and (iv) a processor. The processor is configured to drive the memory device to communicate a predetermined sequence of bit patterns to the controller, and, in response to the sequence of bit patterns, drive the switching unit to connect each one of the external terminals to a respective one of the internal terminals having the bit significance of the memory-device terminal with which the external terminal is in communication. Other embodiments are also described.

Abstract: An apparatus includes a register memory and circuitry. The register memory is configured to hold a minimal value specified for a performance measure of a given type of memory access commands, whose actual performance measures vary among memory devices. The circuitry is configured to receive a memory access command of the given type, to execute the received memory access command in one or more memory devices, and to acknowledge the memory access command not before reaching the minimal value stored in the register memory.

Abstract: A memory device includes a plurality of memory cells, a token input interface, a token output interface and control circuitry. The control circuitry is configured to accept a storage command, to condition execution of at least a part of the storage command on a presence of a token pulse on the token input interface, to execute the storage command, including the conditioned part, in the memory cells upon reception of the token pulse on the token input interface, and to reproduce the token pulse on the token output interface upon completion of the execution.

Abstract: A method includes receiving one or more storage commands and at least one flush command in a storage device, which includes a non-volatile memory and a volatile buffer for buffering data received for storage in the non-volatile memory. The flush command instructs the storage device to commit the data buffered in the volatile buffer to the non-volatile memory. The storage commands are executed in accordance with a first storage rule. The flush command is executed in accordance with a second storage rule having smaller latency relative to the first storage rule.

Abstract: A memory device includes a plurality of memory cells, a token input interface, a token output interface and control circuitry. The control circuitry is configured to accept a storage command, to condition execution of at least a part of the storage command on a presence of a token pulse on the token input interface, to execute the storage command, including the conditioned part, in the memory cells upon reception of the token pulse on the token input interface, and to reproduce the token pulse on the token output interface upon completion of the execution.

Abstract: A memory device includes a plurality of memory cells, a token input interface, a token output interface and control circuitry. The control circuitry is configured to accept a storage command, to condition execution of at least a part of the storage command on a presence of a token pulse on the token input interface, to execute the storage command, including the conditioned part, in the memory cells upon reception of the token pulse on the token input interface, and to reproduce the token pulse on the token output interface upon completion of the execution.

Abstract: A novel mechanism for 1000BASE-T network adapters to detect and resolve connections for cables that are either fully aligned, fully crossed or semi-crossed. The mechanism is applicable to adapters in either master or slave modes, and operates with cables that either have channels A and B aligned with channels C and D crossed or channels A and B crossed and channels C and D aligned. Cables of different configurations can be switched at any time without impacting network operation. In addition, a mechanism for 1000BASE-T adapters to support multiple scrambling methods between the adapter and its link partner is described.

Abstract: A novel mechanism for detecting the presence of powered devices over a network. A unique, infinite pseudo-random sequence of pulses are generated and transmitted over the network to the link partner attached to the other end of the cable. At each time unit, the PSE decides whether or not to transmit a pulse at that time. Thus, the pulses generated have pseudo-random inter-pulse delays between them. In addition, each pulse is pseudo-randomly selected to have either positive or negative polarity. If the link partner is a powered device it will be in loopback mode and the transmitted pulses will be looped back to the transmitter (i.e. the PSE). The PSE, at each time unit regardless of whether or not a pulse was transmitted, opens a search window in which it listens to the RX line for the appropriate expected behavior. If a pulse was transmitted, the PSE expects to see a pulse looped back. Similarly, if no pulse was transmitted, the PSE does not expect to receive a signal during the search window.

Abstract: A novel mechanism for detecting the presence of powered devices over a network. A unique, infinite pseudo-random sequence of pulses are generated and transmitted over the network to the link partner attached to the other end of the cable. At each time unit, the PSE decides whether or not to transmit a pulse at that time. Thus, the pulses generated have pseudo-random inter-pulse delays between them. In addition, each pulse is pseudo-randomly selected to have either positive or negative polarity. If the link partner is a powered device it will be in loopback mode and the transmitted pulses will be looped back to the transmitter (i.e. the PSE). The PSE, at each time unit regardless of whether or not a pulse was transmitted, opens a search window in which it listens to the RX line for the appropriate expected behavior. If a pulse was transmitted, the PSE expects to see a pulse looped back. Similarly, if no pulse was transmitted, the PSE does not expect to receive a signal during the search window.