Abstract: Certain examples described herein relate to printer (110, 210) cooling systems of three-dimensional (3D) printers. In an example of a printer (110, 210) cooling system of a three-dimensional (3D) printer (110, 210), a shared air flow volume (120, 220) is for cooling a plurality of internal printer components (130, 140, 230, 240), and a single air inlet (150, 245) delivers ambient air (160) from outside the three-dimensional (3D) printer (110, 210) to the shared air flow volume (120, 220) In certain cases, the shared air flow volume (120, 220) comprises a first air flow conduit (135, 270) for cooling a first internal printer component (130, 230) and a second air flow conduit (145, 275) for cooling a second internal printer component (140, 240). In certain examples, the first and the second air flow conduits (135, 270) are arranged at least partially in parallel.

Abstract: In one embodiment of the invention, an apparatus for scan testing an integrated circuit is provided. The apparatus includes a combinational logic network; and a device for reducing gate switching in the combinational logic network to reduce power consumption during a scan test on the combinational logic network. The device for reducing gate switching in the combinational logic network includes a device for periodically isolating scan data from the combination logic network; and a device for periodically holding functional data coupled into the combinational network substantially steady. In one embodiment of the invention, the device for reducing gate switching in the combinational logic network is a plurality of serially coupled scan registers each having a pair of opposed controlled outputs with one controlled output providing scan output data and another controlled output providing functional data to the combinational logic network.

Abstract: In one embodiment of the invention, a method of scan testing an integrated circuit is disclosed. The method includes scanning a first test vector and a second test vector sequentially into a plurality of scan registers serially coupled together, each of the plurality of scan registers including a master latch, a scan latch, and a functional latch; and applying the first and the second test vectors sequentially in a delay fault test via the plurality of scan registers to a combinational logic circuit coupled to the plurality of scan registers.

Abstract: An improved scan register and methods of using the same have been disclosed. In one embodiment, the improved scan register includes a master latch having a data input, a data output, and a control input. The control input is coupled to a clock signal. The master latch is operable to store data. The improved scan register further includes a scan latch having a data input, a data output, and a control input. The data input of the scan latch is coupled to the data output of the master latch. The scan latch is operable to receive and to store the data from the master latch in response to the scan latch being in a scan mode. The improved scan register may further include a functional latch having a data input, a data output, and a control input. The data input of the functional latch is coupled to the data output of the master latch. The functional latch is operable to receive and to store the data from the master latch in response to the functional latch being in a functional mode.