Abstract: A message-based processing system is disclosed. An input message received in the message-based processing system comprises a first indication of at least a subset of a plurality of processor elements and a second indication of a target pattern. Each of the plurality of processor elements has an addressable storage entry with a processor element address storing a processor element state. An initial address computation mode is selected from a set of address computation modes. A state value of each of the processor elements in the subset is updated based on magnitude values of respective pattern elements of the target pattern. A currently applied pattern element of the target pattern in each case determines whether to maintain a current address computation mode of the set of address computation modes or assume a next address computation mode selected from the set of address computation modes.

Abstract: A message based processor comprises at least one processor cluster with a plurality of cluster elements each having a respective addressable storage space to store a state value indicative of its state, message handling utilities that are configured to receive input messages that designate specific ones of the plurality of cluster elements, and computation utilities that are configured to update a state value stored in the respective storage element of the designated cluster element. The addressable storage space of each cluster element further stores an operational mode indicator that is indicative of an operational mode of each cluster element. The operational mode is selected from at least one of transmission enabling operational mode and transmission disabling operational mode. The message handling utilities selectively transmit output messages for a cluster element to one or more cluster elements based on the operational mode.

Abstract: A message based processor system (1) with a plurality of message based processor system cores (100) is proposed. Cores therein comprise a processor element controller that is configured to receive a message with an indication of a subset processor elements in the core to which it is directed as well as an indication of a target pattern, and to update the state value of the processor elements (Ei) in the subset in accordance with a specification of the target pattern. The processor element controller (PEC) is configurable in an address computation mode selected from a cyclic set of address computation modes, and configured to maintain its computation mode or assume a next address computation mode selected from the cyclic set dependent on a control value of a currently applied pattern element. Therewith a target pattern can efficiently specified.

Abstract: A processing device may include a message management facility and a message processing facility. The message management facility comprises a first message queue for receiving new instruction messages and a second message queue for receiving rejected instruction messages. The message processing facility receives a first instruction message and a second instruction message from the message management facility. The first instruction message is rejected and returned to the message management facility to add the first instruction message to the second message queue in response to determining that the first instruction message cannot be accepted by a processing device element identified in the first instruction message. Operand data for an input port of a processing device element identified in the second instruction message is retrieved in response to determining that the second instruction message can be accepted by the processing device element identified in the second instruction message.

Abstract: A processing device is described that includes a processing cluster having a message management facility and a message processing facility. The message management facility has a first message queue, a second message queue and a queue controller. The message processing facility has a plurality of processing device elements with at least two input ports, and the message processing facility is configured to: receive the selected instruction messages from the message management facility, accept or reject the selected instruction messages, return rejected selected instruction messages as a bounced instruction message to the message management facility, retrieve operand data from an accepted selected instruction message for an input port of a processing device element identified by the selected instruction message, and perform an operation designated to a processing device element once each of its input ports have received operand data.

Abstract: A message based processor system (1) with a plurality of message based processor system cores (100) is proposed. Cores therein comprise a processor element controller that is configured to receive a message with an indication of a subset processor elements in the core to which it is directed as well as an indication of a target pattern, and to update the state value of the processor elements (Ei) in the subset in accordance with a specification of the target pattern. The processor element controller (PEC) is configurable in an address computation mode selected from a cyclic set of address computation modes, and configured to maintain its computation mode or assume a next address computation mode selected from the cyclic set dependent on a control value of a currently applied pattern element. Therewith a target pattern can efficiently specified.

Abstract: A neural network processor is provided comprising a plurality of mutually succeeding neural network processor layers is provided. A neural network processor layer therein comprising a plurality of neural network processor elements (1) having a respective state register (2) for storing a state value (X) indicative for their state, as well as an additional state register (4) for storing a value (Q) of a state value change indicator that is indicative for a direction of a previous state change exceeding a threshold value. Neural network processor elements in a neural network processor layer are configured to selectively transmit differential event messages indicative for a change of their state, dependent both on the change of their state value and on the value of their state value change indicator.

Abstract: A processing device (1) is provided with at least one processing cluster (100) comprising a message management facility (110) and a message processing facility (120). The message management facility (110) has a first message queue (Q1), a second message queue (Q2) and a queue controller (QCNTRL). The message management facility (110) is to receive new instruction messages (MI) in the first message queue (Q1) and to receive bounced instruction messages (BMI) in the second message queue (Q2). The queue controller Q-CNTRL is to retrieve instruction messages (SMI) from a designated one of the first message queue (Q1) and the second message queue (Q2).

Abstract: A method and system for classifying image content in a sequence (SEQ) of image frames. Frame image data (FI), representing an appearance of image content of the image frames (Fm,Fn), is converted into frame event data (FEn). The conversion comprises determining, for each event, a set of event parameters. The event parameters include positional coordinates (x,y) representing a corresponding position of the respective image content in the frame image data (FI) having changed value between different image frames (Fm,Fn) in the sequence (SEQ). The event parameters of the frame event data (FEn) are processed, preferably by clustering, to determine at least one event-based region of interest (R1) in the sequence (SEQ) of image frames. At least one classification (C1) is calculated based on an intersection of the event-based region of interest (R1) with the frame image data (FI) of an image frame (Fn) in the sequence (SEQ).

Abstract: A neuromorphic processing system (1) is disclosed comprising a plurality of neuromorphic processing clusters (100) coupled to a message exchange network (20) for exchange of event messages. A neuromorphic cluster therein comprises a message receiving facility (110) to receive event messages from the message exchange network, a message transmitting facility (120) to transmit event messages via the message exchange network and a neuromorphic processor (130) having a set of state memory entries (10 j) for storing a value representative of a neuromorphic state associated with a neuromorphic element and a computation facility (134) to update the neuromorphic state associated with neuromorphic elements that are indicated as the destination of the event message. The message receiving facility (110) and/or the message transmitting facility (120) are enhanced to enable message distribution according to a pattern.

Abstract: A neuromorphic processor and a neuromorphic processing method are provided comprising plurality of neuromorphic elements (i=1, i=n), a message exchange facility (20), and a computation unit (30). The plurality of neuromorphic elements has a respective state memory entry (10_j) for storing their state. The message exchange facility (20) enables neuromorphic elements to transmit neural event messages, and to receive transmitted neural event messages, a neural event message including an indication (NA) of one or more neuromorphic elements selected as the destination, a message type (MT) and one or more message parameters (MP1, . . . , MPm). The computation unit (30) is to update the state dependent on received neural event messages. The message type is one of at least an accumulation message (A) and a leakage message (L).

Abstract: One or more tasks to be executed on one or more processors are formulated into a graph, with dependencies between the tasks defined as edges in the graph. In the case of a Radio Access Technology (RAT) application, the graph is iterative, whereby each task may be activated a number of times that may be unknown at compile time. A discrete number of allowable frequencies for processors while executing tasks are defined, and the power dissipation of the processors at those frequencies determined. A linear programming problem is then formulated and solved, which minimizes the overall power dissipation across all processors executing all tasks, subject to several constraints that guarantee complete and proper functionality. The switching of processors executing the tasks between operating points (frequency, voltage) may be controlled by embedding instructions into the tasks at design or compile time, or by a local supervisor monitoring execution of the tasks.

Abstract: One or more tasks to be executed on one or more processors are formulated into a graph, with dependencies between the tasks defined as edges in the graph. In the case of a Radio Access Technology (RAT) application, the graph is iterative, whereby each task may be activated a number of times that may be unknown at compile time. A discrete number of allowable frequencies for processors while executing tasks are defined, and the power dissipation of the processors at those frequencies determined. A linear programming problem is then formulated and solved, which minimizes the overall power dissipation across all processors executing all tasks, subject to several constraints that guarantee complete and proper functionality. The switching of processors executing the tasks between operating points (frequency, voltage) may be controlled by embedding instructions into the tasks at design or compile time, or by a local supervisor monitoring execution of the tasks.

Abstract: A processing system according to the invention comprises a plurality of processing elements (PE1, . . . , PE7). The processing elements comprise a controller and computation means. The plurality of processing elements is dynamically reconfigurable as mutually independently operating task units (TU1, TU2, TU3), which task units comprise one processing element (PE7) or a cluster of two or more processing elements (PE3, PE4, PE5, PE6). The processing elements within a cluster are arranged to execute instructions under a common thread of program control. In this way the processing system is capable of using the same sub-set of data-path elements to exploit instruction level parallelism or task level parallelism or a combination thereof, dependent on the application.

Abstract: A method is disclosed for partitioning a specification in a source code. In a first step, the specification is converted into a plurality of abstract syntax trees. In a second step, the plurality of abstract syntax trees is partitioned into at least a first set and a second set. The first set of abstract syntax trees is to be implemented by a first processor and the second set of abstract syntax trees is to be implemented by a second processor. The first and second set of abstracts syntax trees are translated to a specification in the original source code language, respectively, allowing the user to add manual changes to the specifications. Furthermore, specific compiler and design tools are used to convert the specifications into corresponding executable machine code and a specification of the co-processor.