Abstract: Task execution among a plurality of processors that are configured to operate concurrently at a same global Voltage/Frequency (VF) level is controlled by using a global power manager to control VF switching from one VF level to another VF level, the same current VF level governing VF settings of each processor. Each of the processors controls whether it will wait for a VF switch from a current VF level to a next VF level prior to enabling execution of a next scheduled task for the one of the processors, with the decision being based on whether a current VF level is higher than the next scheduled VF level. The global power manager performs VF level switching at least based on a timing schedule, and in some but not all embodiments, also on whether all processors indicate that they are waiting for a VF level switch.

Abstract: Task execution among a plurality of processors that are configured to operate concurrently at a same global Voltage/Frequency (VF) level is controlled by using a global power manager to control VF switching from one VF level to another VF level, the same current VF level governing VF settings of each processor. Each of the processors controls whether it will wait for a VF switch from a current VF level to a next VF level prior to enabling execution of a next scheduled task for the one of the processors, with the decision being based on whether a current VF level is higher than the next scheduled VF level. The global power manager performs VF level switching at least based on a timing schedule, and in some but not all embodiments, also on whether all processors indicate that they are waiting for a VF level switch.

Abstract: A processor system is described comprising at least a first and a second processor element (PEI, PE2). The first processor element (PEI) has a cluster request indicator (CR12) related to the second processor element and the second processor element (PE2) has a cluster request indicator (CR21) related to the first processor element. The processor elements have an instruction set enabling dynamic control of the indicators. The indicators (CR12, CR21) have a value range comprising at least a first value (positive indicator) indicating that the processor element requests to form a cluster with the related processor element, and a second value (negative indicator) indicating that the processor element does not request to form a cluster with the related processor element. The system further comprises a cluster control facility (CC12) which detects the value of the cluster request indicator and organizes the processor elements in clusters in accordance with the detected values.

Abstract: A processing system according to the invention comprises a plurality of processing elements (PE1, . . . ,PE7). The processing elements comprise a controller and computation means. The plurality of processing elements is dynamically reconfigurable as mutually independently operating task units (TU1, TU2, TU3), which task units comprise one processing element (PE7) or a cluster of two or more processing elements (PE3, PE4, PE5, PE6). The processing elements within a cluster are arranged to execute instructions under a common thread of program control. In this way the processing system is capable of using the same sub-set of data-path elements to exploit instruction level parallelism or task level parallelism or a combination thereof, dependent on the application.

Abstract: The basic idea of the invention is to provide a clustered ILP processor based on a fully-connected inter-cluster network with a non-uniform latency. A clustered Instruction Level Parallelism processor is provided. Said processor comprises a plurality of clusters (C1-C6) each comprising at least one register file (RF) and at least one functional unit (FUI), wherein said clusters (C1-C6) are fully-connected to each other; and wherein the latency of the connections between said clusters (C1-C6) depends on the distance between said clusters (C1-C6).

Abstract: The basic idea of the invention is to add switches along a bus, in order divide the bus into smaller independent segments by opening/closing said switches. A clustered Instruction Level Parallelism processor comprises a plurality of clusters (C1-C6) each comprising at least one register file (RF) and at least one functional unit (FU), a bus means (100) for connecting said clusters (C1-C6), wherein said bus (100) comprises a plurality of bus segments (100a, 100b, 100c), and switching means (200), which is arranged between adjacent bus segments (100a, 100b, 100c). Said switching means (200) are used for connecting or disconnecting adjacent bus segments (100a, 100b, 100c). Furthermore, a method for accessing a bus (100) in a clustered Instruction Level Parallelism processor is shown. Said bus (100) comprises at least one switching means (200) along said bus (100).

Abstract: Target systems combining a number of different processors, for example a general-purpose processor (GP) and at least one co-processor (COP), or alternatively two or more co-processors (COPA, COPB, COPC), allow combining flexibility and speed for execution of a set of functions. The design of such target systems requires partitioning of a specification in a part to be implemented by the general-purpose processor and a part to be implemented by a co-processor, or into several parts to be implemented by different co-processors. The present invention describes a method for partitioning a specification in a source code. In a first step, the specification 301 is converted into a plurality of abstract syntax trees 101. In a second step, the plurality of abstract syntax trees 101 is partitioned into at least a first set 201 and a second set 203.