Abstract: A computer system merges data variables to be written into the same memory address. The data variables are merged by generating mask bits corresponding to the positions of the data variables within an addressable memory location. The data variables and the mask bits are merged as long as a condition for not merging the data variable is satisfied. For example, the data to be written is directed to a different address or if a read request becomes dependent on a pending write request, a write memory cycle is initiated to write the merged data into the memory.

Abstract: A method of accessing data from a plurality of DSUs allows for data to be accessed over a bi-directional data bus at full bus speed. If the execution of a bus cycle requires switching bus drivers that drive the data bus, a dummy cycle is executed before valid data may be presented on the bus. The execution of dummy cycle ahead of presenting data on the data bus allows for the elapse of a bus settlement time associated with physical properties of the data bus, thereby making it possible to operate the data bus at full speed.

Abstract: In a computer system, the number of memory cycles for reading data is reduced. Read requests for data from a memory location are received at a data storage controller. A determination is made as to whether a read request is dependent on a pending write request that modifies the memory location. If so, a memory cycle is executed that initiates a read cycle for reading the data at the memory location, modifies the read data according to the pending write request, and initiates a write cycle that writes the modified data into the memory location. Then, the dependent read request is serviced, without initiating another read cycle, by returning the modified data to the memory controller prior to initiating the write cycle.