Abstract: A system and method for securing configuration information for a computer system. The method comprises saving configuration information in CMOS memory and automatically programming that configuration information into a non-volatile memory. The system includes a processor, a CMOS memory, and a flash memory. The system also includes a computer-readable medium having computer-executable instructions stored therein for causing configuration information, when saved to the CMOS memory, to be automatically programmed into the flash memory and for causing configuration information stored in the flash memory to be automatically retrieved from the flash memory and written into the CMOS memory every time the computer system is powered on or reset.

Abstract: A method for updating firmware. The method includes providing replaceable information in a non-modifiable storage and replacement information in a modifiable storage or a removable storage and providing a replacement indicator. The replacement information is accessed instead of the replaceable information based upon the replacement indicator.

Abstract: An apparatus includes a configuration selector that is selectively configurable to denote one of a plurality of operating modes for the apparatus, including a configuration mode. The apparatus further comprising a programmable multiplexer, a processor, a bus, and a storage medium having stored therein a basic input/output system (BIOS) equipped to operate in any one of the plurality of operating modes, including the configuration mode wherein the BIOS facilitates user programming of a plurality of operating parameters for the apparatus. The programmable multiplexer, responsive to the configuration selector, asserts a default bus/core ratio common to a plurality of processors and buses that can be employed to form the apparatus when the configuration selector is configured to denote the configuration mode of operation. The processor, coupled to the storage medium and the programmable multiplexer, operates to execute the BIOS, in a speed consistent with the asserted bus/core ratio.

Abstract: An apparatus includes a storage medium having stored therein a segmented basic input/output system (BIOS) divided among a plurality of segments within the storage medium, and a processor operative to execute the segmented BIOS. In accordance with the teachings of the present invention, the BIOS includes a recovery function that is mode dependent in that while the apparatus is in an update mode the recovery function executes a full reflash of all relevant segments of the segmented BIOS, whereas while the apparatus is in a normal mode the recovery function executes a partial reflash of only identified corrupted BIOS segments.

Abstract: An apparatus includes a configuration selector that is selectively configurable to denote one of a plurality of operating modes for the apparatus, including a configuration mode. The apparatus further comprising a programmable multiplexer, a processor, a bus, and a storage medium having stored therein a basic input/output system (BIOS) equipped to operate in any one of the plurality of operating modes, including the configuration mode wherein the BIOS facilitates user programming of a plurality of operating parameters for the apparatus. The programmable multiplexer, responsive to the configuration selector, asserts a default bus/core ratio common to a plurality of processors and buses that can be employed to form the apparatus when the configuration selector is configured to denote the configuration mode of operation. The processor, coupled to the storage medium and the programmable multiplexer, operates to execute the BIOS, in a speed consistent with the asserted bus/core ratio.

Abstract: A method and apparatus for protecting data using lock values in a computer system includes indicating that the computer system does not support locked accesses to the data. However, upon receipt of a request to write to the storage area where the data is contained, the present invention checks whether a lock value corresponding to the request matches a predetermined lock value. If the lock value matches the predetermined lock value, then the data is written to the storage area; otherwise, the storage area is left unmodified.

Abstract: A request is received from a caller to perform a read of data from a storage area of a computer system, the data having master header data in a header portion. The master header data is replaced with alternate header data before returning the data to the caller. The data, including the alternate header data, is returned to the caller. A request is received from the caller to perform a write of caller data to the storage area, the caller data having caller header data in a header portion of the caller data. The write of caller data is allowed only if the caller header data is identical to the master header data.

Abstract: A status parameter is set for a storage area of a computer system to a read-only status. An access key is received from an access key call by a caller. The status parameter is changed to a write-permissible status if the access key matches a master access key. A request to perform a write to the storage area is received, and the write is allowed only if the status parameter has been set to the write-permissible status. The status parameter is reset to the read-only status after the write is performed.

Abstract: A request to erase a storage area of a computer system is received via an erase call by a caller, the erase call containing an erasure key. The storage area is erased only if the erasure key matches a master erasure key corresponding to the storage area. A request is received to perform a write to the storage area, and the write is allowed only if the storage area has been erased.

Abstract: A method and apparatus for protecting data using lock values in a computer system includes indicating that the computer system does not support locked accesses to the data. However, upon receipt of a request to write to the storage area where the data is contained, the present invention checks whether a lock value corresponding to the request matches a predetermined lock value. If the lock value matches the predetermined lock value, then the data is written to the storage area; otherwise, the storage area is left unmodified.

Abstract: A computer system wherein a portion of code/data stored in a non-volatile memory device can be dynamically modified or updated without removing any covers or parts from the computer system. The computer system of the preferred embodiment includes a flash memory component coupled to a computer system bus for storing non-volatile code and data. Using the present invention, the contents of a portion of the flash memory may be replaced, modified, updated, or reprogrammed without the need for removing and/or replacing any computer system hardware components. The flash memory device used in the preferred embodiment contains four separately erasable/programmable non-symmetrical blocks of memory. One of these four blocks may be electronically locked to prevent erasure or modification of its contents once it is installed. This configuration allows the processing logic of the computer system to update or modify any selected block of memory without affecting the contents of other blocks.

Abstract: A computer system wherein a paging technique is used to expand the useable non-volatile memory capacity beyond a fixed address space limitation. The computer system of the preferred embodiment includes a flash memory component for storing non-volatile code and data including a system BIOS in the upper 128K of memory. The useful BIOS memory space is effectively increased while maintaining the address boundary of the upper 128K region. The address space of the non-volatile memory device is logically separated into distinct pages of memory (Pages 1-4). Using the apparatus and techniques of the present invention, Page 1, Page 3 and Page 4 may be individually swapped into the address space originally occupied by Page 1 (the swappable page area). In the preferred embodiment, Page 2 is held static and thus is not used as a swap area. Each of the swappable pages, Page 1, Page 3, and Page 4, contain processing logic called swapping logic used during the swapping or paging operation.

Abstract: A hardware timer dedicated to the BIOS which operates independent of the CPU timer. The BIOS activates the timer by writing a delay count to a predetermined port. Address decode circuitry identifies an address match to a write port address. When an address match coincides with a write command from the BIOS, write control circuitry coupled to the address decode circuitry activates a "load" signal for loading the delay count into a counter circuit. The counter circuit, which is coupled to the write control circuitry, operates on a clock having frequency independent of the CPU operating frequency. The counter circuit comprises a flip-flop that synchronizes the "load" signal to the clock of the counter circuit. The synchronized "load" signal causes the delay count to be loaded into the counter circuit. The write control circuitry inactivates the "load" signal such that the delay count is loaded exactly once. The counter circuit counts when the synchronized "load" signal is inactive.

Abstract: A computer system wherein a paging technique is used to expand the usable non-volatile memory capacity beyond a fixed address space limitation. The computer system of the preferred embodiment includes a flash memory component for storing non-volatile code and data including a system BIOS in the upper 128K of memory. The useful BIOS memory space is effectively increased while maintaining the address boundary of the upper 128K region. The address space of the non-volatile memory device is logically separated into distinct pages of memory (Pages 1-4). Page 1, Page 3 and Page 4 may be individually swapped into the address space originally occupied by Page 1 (the swappable page area). In the preferred embodiment, Page 2 is held static and thus is not used as a swap area. Each of the swappable pages contain processing logic called swapping logic used during the swapping or paging operation. The swapping logic operates in conjunction with paging hardware to effect the swapping of pages into the swappable page area.