Abstract: A semiconductor integrated circuit device having a test circuit for testing a plurality of gate cells arranged in a matrix; and connected to constitute a logic circuit. A plurality of row selection wires are provided along the gate cells in a row direction, each of the gate cells being operatively connected to a row selection wire, and a plurality of column read-out wires are provided along the gate cells in a column direction, outputs of each of the gate cells being operatively connected to column read-out wires. A row selection ring counter, operatively connected to the row selection wires, selects any of the row selection wires and any of the gate cells connected to the selected row selection wire so that a data selector and ring counter read the output of each gate cell arranged in the logic circuits through the column read-out wires.

Abstract: A complementary logic circuit which has large power handling capacity, high switching speed and still has low power consumption is disclosed. The circuit is composed of a first stage comprising a complementary MIS-FET, and an output stage comprising complementary bipolar transistors or complementary vertical FETs. The output stage is provided with pull-up and pull-down elements, which pull up or pull down the amplitude of the output signal almost equal to that of the power supply voltages. Accordingly, the lack of sufficient amplitude in the conventional Bi-MIS circuit to drive the C-MIS circuit is improved, and it secures the stable operation of C-MIS logic circuits.

Abstract: A logical gate circuit includes an emitter-grounded switching transistor and a pull-up circuit connected to a collector of the switching transistor. The switching transistor is cut OFF when an input signal has a high level and is turned ON when the input signal has a low level. A control MIS transistor is connected to a base of the switching transistor and is turned ON and OFF in response to respective low and high levels, of the output terminal of the switching transistor. An input transistor is connected in series with the control MIS transistor and is turned ON and OFF when the input signal is high and low, respectively. Thus, the logical gate circuit allows current to flow only during a transient signal period.

Abstract: A complementary logic circuit which has large power handling capacity, high switching speed and still has low power consumption is disclosed. The circuit of the present invention is composed from a first stage comprising a complementary MIS-FET, and an output stage comprising a complementary vertical FET. The gate of the V-FET is arranged so as to serve as the drain or source of the MIS-FET. In such an arrangement, the steps of fabricating the IC are reduced and the packing density is increased. By varying the connection of positive and negative voltage sources, the circuit can be operated as an inverting or non-inverting logic circuit.

Abstract: A method for manufacturing a gate array IC device in which the turn-around time on design is short, the system design is simple, and the memory area for designing is reduced. The method includes manufacturing a master bulk pattern of a basic cell array on the semiconductor substrate, and storing, in semi-permanent memory, symbol data and detailed data for standard macro cells and standard expanded macro cells prior to designing a logic system. Each macro cell comprises one or more basic cells and has a basic logic function. Each expanded macro cell comprises plural macro cells and has a more complicated and sophisticated logic function than the macro cells. In addition, the logic functions of the expanded macro cells are standard in the logic system design technology area. When a designer creates a logic system, only symbol data for the macro cells and the expanded macro cells, and the connections thereof are used and stored in the memory, so that it is relatively easy to design the system.

Abstract: A TTL fundamental logic circuit comprising an npn-type input transistor, an npn-type output transistor, and a pnp-type output transistor. The pnp-type output transistor has an emitter connected to the collector of the npn-type output transistor, a base connected to the base of the npn-type output transistor and a collector that is grounded. The pnp-type output transistor is turned on when the npn-type output transistor is turned off, thereby the potential of the high level output signal is decreased, and the propagation delay of the fundamental logic circuit is reduced.