Abstract: A decoder is provided for decoding variable word length (VWL) encoded serial data in which each non-zero word comprises a start bit and an end bit of one state and a number of intervening bits of a different state, the number of such bits representing the magnitude of the word. The decoder comprises a binary counter and means responsive to a start bit of an input word for clearing the counter; responsive to any intervening bits present to enable the counter to count such intervening bits; and responsive to an end bit of said variable word to output the contents of the counter as a parallel binary word.Where the number of intervening bits is one less than the actual magnitude the decoder may include means for adding one to the counter output.The decoder may also detect an additional bit in the input word, representing, for example, its polarity, and provide a corresponding bit in the fixed-length output word.

Abstract: An encoder is provided for encoding fixed length binary words into (VWL) encoded serial data in which each non-zero word comprises a start bit and an end bit of one state and a number of intervening bits of a different state, the number of such bits representing the magnitude of the word. In a preferred embodiment the coder comprises a multiplexer, a PROM and a flip-flop. The PROM provides a feedback signal comprising three parts - a control signal, a binary word representing the magnitude of the input word, and an output signal having either of two states. The feedback signal is repeatedly applied to the PROM by the multiplexer.The PROM responds by reducing the magnitude part of the feedback signal by one. Each time the cycle repeats, another bit appears at the output of the coder as the output signal. Accordingly, the number of such output bits corresponds to the magnitude of the input word. Eventually, when the magnitude has been reduced to zero, the multiplexer selects a new word to apply to the PROM.