Patents by Inventor Osama Shana'a

Osama Shana'a has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wideband highly-linear low output impedance D2S buffer circuit
    Patent number: 9893728
    Abstract: A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: February 13, 2018
    Assignee: MEDIATEK INC.
    Inventors: Fei Song, Osama Shana'a, Yuen Hui Chee
  • Wideband Highly-Linear Low Output Impedance D2S Buffer Circuit
    Publication number: 20160365859
    Abstract: A wideband highly-linear buffer circuit exhibiting a low output impedance comprises a first PFET (PFET1), a second PFET (PFET2), a first NFET (NFET1), and a second NFET (NFET2). Sources of PFET1 and PFET2 are coupled to VDD. PFET1's drain is coupled to an output lead. PFET2 acts as a current source. NFET1's drain is coupled to PFET2's drain and to PFET1's gate. NFET1's source is coupled to the output lead. NFET2's source is coupled to ground. NFET2's drain is coupled to NFET1's source and to the output lead. NFET1's gate is AC coupled to a first input lead. In a single-ended input example, NFET2's gate is AC coupled NFET1's drain. In a differential input example, NFET2's gate is AC coupled to a second input lead. In another differential input example, PFET2 is not just a current source, but rather PFET2's gate is AC coupled to the first input lead.
    Type: Application
    Filed: September 23, 2015
    Publication date: December 15, 2016
    Inventors: Fei Song, Osama Shana'a, Yuen Hui Chee
  • Linearized transconductance cell
    Patent number: 6329865
    Abstract: A transconductance cell has first and second transistors, each transistor having a control terminal and first and second terminals. A signal is output from the second transistor in response to a voltage input applied to the control terminal of the first transistor. The transconductance cell includes a linear element coupled between the first terminal of the first transistor and the first terminal of the second transistor. A tank circuit is coupled between a reference potential and a node between the linear element and the first terminal of the second transistor.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: December 11, 2001
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Johannes J. E. M. Hageraats, Osama Shana'a