Patents by Inventor Osamu Baba

Osamu Baba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240110719
    Abstract: An air conditioning control device includes: an operation pattern acquiring unit to acquire operation patterns indicating an operation target air conditioner in a room; a temperature data acquiring unit to acquire temperature data indicating a temperature measured by a temperature sensor when the air conditioner is in operation: a prediction model generating unit to generate, using a control amount of the air conditioner and temperature data acquired when the air conditioner is in operation as training data, a room-temperature prediction model for predicting the temperature measured by the temperature sensor when the air conditioner are in operation; and an operation pattern selecting unit to provide the control amount of the air conditioner to the room-temperature prediction model to acquire a prediction temperature from each of the room-temperature prediction models, and selects one operation pattern from the operation patterns on the basis of the prediction temperature.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 4, 2024
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroaki HOKARI, Koki NAKANE, Toshisada MARIYAMA, Naoyuki MIYAZAKI, Osamu HASEGAWA, Wataru BABA
  • Publication number: 20190033714
    Abstract: An object of the present invention is to provide a resin composition capable of suppressing surface roughness in a thin film portion and maintaining insulation reliability of a thin film portion, a cured relief pattern of the resin composition, and a method for manufacturing a semiconductor electronic component or a semiconductor equipment using the cured relief pattern. The constitution of the present invention for achieving the above-mentioned object is as follows. That is, the present invention provides a resin composition containing: (a) at least one resin selected from an alkali-soluble polyimide, an alkali-soluble polybenzoxazole, an alkali-soluble polyamide-imide, precursors thereof, and copolymers thereof; and (b) an alkali-soluble phenol resin, wherein a ratio (Rb/Ra) between an alkali dissolution rate (Ra) of the resin (a) and an alkali dissolution rate (Rb) of the resin (b) satisfies a relationship of 0.5?Rb/Ra?2.0.
    Type: Application
    Filed: January 24, 2017
    Publication date: January 31, 2019
    Applicant: TORAY INDUSTRIES, INC.
    Inventors: Osamu BABA, Makoto HAYASAKA, Ryoji OKUDA
  • Patent number: 9449920
    Abstract: An electronic device is disclosed. The electronic device comprises a transistor provided on a substrate, a transmission line provided on the substrate and connected to the transistor, an electrode pad connected to the transmission line, and a connection wiring electrically connecting the electrode pad and the transmission line through a first wiring and a second wiring. Both of the first wiring and the second wiring are connected to different positions of the electrode pad.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: September 20, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Osamu Baba, Takeshi Kawasaki
  • Publication number: 20160013130
    Abstract: An electronic device is disclosed. The electronic device comprises a transistor provided on a substrate, a transmission line provided on the substrate and connected to the transistor, an electrode pad connected to the transmission line, and a connection wiring electrically connecting the electrode pad and the transmission line through a first wiring and a second wiring. Both of the first wiring and the second wiring are connected to different positions of the electrode pad.
    Type: Application
    Filed: July 7, 2015
    Publication date: January 14, 2016
    Inventors: Osamu Baba, Takeshi Kawasaki
  • Patent number: 8543078
    Abstract: A circuit includes: a first line to which input and output signal terminals are connected; a first transistor having a first terminal connected to the first line, a second terminal connected to a ground potential, and a control terminal supplied with a first oscillation signal, the first transistor outputting the first signal and its harmonic component; a second transistor having a first terminal connected to the first line, a second terminal connected to the ground potential, and a control terminal supplied with a second oscillation signal, the second transistor outputting the second signal and its harmonic component; a first harmonic generator connected to the control terminal of the first transistor and generates a harmonic component including the harmonic component by the first transistor; and a second harmonic generator connected to the control terminal of the second transistor and generates a harmonic component including the harmonic component by the second transistor.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: September 24, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Osamu Anegawa, Osamu Baba, Miki Kubota, Tsuneo Tokumitsu
  • Patent number: 8519805
    Abstract: An electronic circuit includes a first transmission line connected to a DC power source, a second transmission line having one end connected to the first transmission line at a connecting node, a narrow portion formed in the second transmission line and provided at a position that is away from a specific position by equal to or greater than ? wavelength of a signal, the specific position being away from the connecting node at a distance equal to ¼ wavelength, and a capacitor having one end connected to the other end of the second transmission line and the other end connected to a reference potential.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: August 27, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Osamu Baba
  • Patent number: 8264279
    Abstract: An electronic circuit includes a first transistor having a first terminal grounded, a second transistor having a control terminal coupled with a second terminal of the first transistor, a first terminal grounded via a first capacitor, and a second terminal to which a DC power supply is connected, a first distributed constant line having one end connected to a first node between the second terminal of the first transistor and the control terminal of the second transistor and another end grounded via a second capacitor, a second distributed constant line having one end connected to the second terminal of the first transistor and another end connected to the first node, a third distributed constant line having one end connected to the control terminal of the second transistor and another end connected to the first node, a resistor connected between a second node between the first line and the second capacitor and a third node between the first terminal of the second transistor and the first capacitor, and a path
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: September 11, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Osamu Anegawa, Osamu Baba, Miki Kubota, Tsuneo Tokumitsu
  • Publication number: 20120105169
    Abstract: An electronic circuit includes a first transmission line connected to a DC power source, a second transmission line having one end connected to the first transmission line at a connecting node, a narrow portion formed in the second transmission line and provided at a position that is away from a specific position by equal to or greater than ? wavelength of a signal, the specific position being away from the connecting node at a distance equal to ¼ wavelength, and a capacitor having one end connected to the other end of the second transmission line and the other end connected to a reference potential.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 3, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Osamu Baba
  • Publication number: 20120026109
    Abstract: A mobile terminal device includes: a touch panel in which one of a plurality of segment areas is adjacent to the other segment areas different in at least three directions; a pattern storing unit that associates and stores any of functions of the mobile terminal device with a registered pattern formed of the plurality of adjacent segment areas of the segment areas of the touch panel; a pattern recognizing unit that recognizes the plurality of segment areas continuously touched by a user, as an input pattern; and a function activating unit that compares the input pattern recognized by the pattern recognizing unit with the registered pattern stored in the pattern storing unit, and activates the function corresponding to the registered pattern when the input pattern matches the registered pattern.
    Type: Application
    Filed: April 26, 2010
    Publication date: February 2, 2012
    Inventor: Osamu Baba
  • Publication number: 20110241739
    Abstract: A circuit includes: a first line to which input and output signal terminals are connected; a first transistor having a first terminal connected to the first line, a second terminal connected to a ground potential, and a control terminal supplied with a first oscillation signal, the first transistor outputting the first signal and its harmonic component; a second transistor having a first terminal connected to the first line, a second terminal connected to the ground potential, and a control terminal supplied with a second oscillation signal, the second transistor outputting the second signal and its harmonic component; a first harmonic generator connected to the control terminal of the first transistor and generates a harmonic component including the harmonic component by the first transistor; and a second harmonic generator connected to the control terminal of the second transistor and generates a harmonic component including the harmonic component by the second transistor.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 6, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Osamu Anegawa, Osamu Baba, Miki Kubota, Tsuneo Tokumitsu
  • Publication number: 20110181363
    Abstract: An electronic circuit includes a first transistor having a first terminal grounded, a second transistor having a control terminal coupled with a second terminal of the first transistor, a first terminal grounded via a first capacitor, and a second terminal to which a DC power supply is connected, a first distributed constant line having one end connected to a first node between the second terminal of the first transistor and the control terminal of the second transistor and another end grounded via a second capacitor, a second distributed constant line having one end connected to the second terminal of the first transistor and another end connected to the first node, a third distributed constant line having one end connected to the control terminal of the second transistor and another end connected to the first node, a resistor connected between a second node between the first line and the second capacitor and a third node between the first terminal of the second transistor and the first capacitor, and a path
    Type: Application
    Filed: January 25, 2011
    Publication date: July 28, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Osamu Anegawa, Osamu Baba, Miki Kubota, Tsuneo Tokumitsu
  • Patent number: 7561001
    Abstract: An electronic circuit device includes a negative resistance generating circuit, a second transistor and a path. The negative resistance generating circuit has a first transistor having a control terminal coupled to a resonator. The second transistor has a control terminal coupled to an output terminal of the first transistor and has an output terminal coupled to a DC bias terminal. The path is coupled to between the DC bias terminal and an output terminal of the first transistor through the second transistor and provides a bias to the first transistor.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: July 14, 2009
    Assignee: Eudyna Devices Inc.
    Inventors: Tsuneo Tokumitsu, Osamu Baba
  • Publication number: 20080048764
    Abstract: An electronic circuit device includes a negative resistance generating circuit, a second transistor and a path. The negative resistance generating circuit has a first transistor having a control terminal coupled to a resonator. The second transistor has a control terminal coupled to an output terminal of the first transistor and has an output terminal coupled to a DC bias terminal. The path is coupled to between the DC bias terminal and an output terminal of the first transistor through the second transistor and provides a bias to the first transistor.
    Type: Application
    Filed: July 26, 2007
    Publication date: February 28, 2008
    Applicant: EUDYNA DEVICES INC.
    Inventors: Tsuneo Tokumitsu, Osamu Baba
  • Patent number: 6900482
    Abstract: A high-frequency semiconductor device for power amplification has a comb-teeth electrode on each of active regions formed on the front surface of the semiconductor substrate. One aspect of the present invention, there is provided a monolithic microwave integrated circuit (MMIC) having a plurality of rectangular-shaped active regions arranged side by side on the front surface of the semiconductor substrate, each of the active regions having interdigited gate, drain and source electrodes thereon which are connected to the respective pads by multilayer interconnection technique. Additionally, the source potential is fed from the back surface of the substrate through a metal plugged via-hole.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: May 31, 2005
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Yoshio Aoki, Yutaka Mimino, Osamu Baba, Muneharu Gotoh
  • Patent number: 6853054
    Abstract: A high frequency semiconductor device including wiring layers which are formed above a semiconductor substrate and in which transmission lines are formed by combining with a ground plate having a potential fixed at the ground potential, at least one crossing portion in which the wiring layers mutually cross, with insulating interlayers provided therebetween, and at least one separation electrode being selectively provided on one of the insulating interlayers, the at least one separation electrode having a potential fixed at the ground potential. Accordingly, in the high frequency semiconductor device, electrical interference between two crossing wiring layer is prevented and transmission loss is suppressed.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: February 8, 2005
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Osamu Baba, Yutaka Mimino
  • Patent number: 6825809
    Abstract: A structure for eliminating the influence of an antenna line connected to the patch electrode on the antenna characteristics of a patch antenna built in an MMIC is disclosed. A through-hole is formed in the antenna ground plane which is provided under the patch electrode with an interlayer insulation film therebetween, the antena line is provided in the side opposite to the patch electrode with respect to the antena ground plane, and the patch electrode and antenna line are connected to each other with a conductor passing through the trough-hole.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: November 30, 2004
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Yoshio Aoki, Yutaka Mimino, Osamu Baba, Muneharu Gotoh
  • Patent number: 6787909
    Abstract: A structure for preventing MMICs (Monolithic Microwave Integrated Circuits) from deterioration in the high-frequency transmission characteristics thereof, which results from mechanical pressure applied to the pads during the wire-bonding thereto for external connection. The structure includes a groove provided in the surface of the interlayer insulation film around each of the pads. The line conductor for transmitting high-frequency signals is free from the peeling off or bending thereof, which is caused by the deformation in the interlayer insulation films during when the mechanical pressure applied to the pads, and thus, the change in the transmission characteristics of the line conductor can be minimized, and the reliability of MMICs can be improved.
    Type: Grant
    Filed: March 1, 2002
    Date of Patent: September 7, 2004
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Yutaka Mimino, Osamu Baba, Yoshio Aoki, Muneharu Gotoh
  • Patent number: 6774484
    Abstract: A multilayer wiring structure for MMICs includes a power-supply wiring formed of a multilayer wiring (a plurality of power-supply lines). The wires are interconnected by throughholes. A power-supply current is divided and supplied to the lines. A large current can be supplied to the entirety of the multilayer wiring, even when the width of each of the lines is reduced. The multilayer wiring structure has an improved degree of freedom in the layout of wiring.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: August 10, 2004
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Yutaka Mimino, Osamu Baba, Yoshio Aoki, Muneharu Gotoh
  • Patent number: 6747299
    Abstract: A high frequency semiconductor device includes a ground plate, an insulating layer, a power-supply conductor, an insulating interlayer, and a strip line as a line conductor. The power-supply conductor is disposed above the ground plate, with the insulating layer provided therebetween. The ground plate and the power-supply conductor have a capacitance formed therebetween. Thus, the line conductor regards the power-supply conductor as having a potential identical to that of the ground plate. This makes it possible to lay out the line conductor without considering the arrangement of the power-supply conductor. In other words, by two-dimensionally overlapping a microstrip line and a power-supply conductor in an MMIC, the degree of freedom in the device layout can be increased.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: June 8, 2004
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Yutaka Mimino, Osamu Baba, Yoshio Aoki, Muneharu Gotoh
  • Patent number: 6712284
    Abstract: In a high frequency semiconductor device, a shield plate which is connected to the ground potential is provided above an MMIC structure including line conductors, with an insulating interlayer provided therebetween. By using the shield plate to shield the MMIC, interference caused by external electromagnetic waves or leakage of electromagnetic waves to the exterior can be reduced in a chip alone.
    Type: Grant
    Filed: March 6, 2002
    Date of Patent: March 30, 2004
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Yoshio Aoki, Yutaka Mimino, Osamu Baba, Muneharu Gotoh