Patents by Inventor Osamu Fukuoka

Osamu Fukuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8860081
    Abstract: To improve the performance of a protection circuit including a diode formed using a semiconductor film. A protection circuit is inserted between two input/output terminals. The protection circuit includes a diode which is formed over an insulating surface and is formed using a semiconductor film. Contact holes for connecting an n-type impurity region and a p-type impurity region of the diode to a first conductive film in the protection circuit are distributed over the entire impurity regions. Further, contact holes for connecting the first conductive film and a second conductive film in the protection circuit are dispersively formed over the semiconductor film. By forming the contact holes in this manner, wiring resistance between the diode and a terminal can be reduced and the entire semiconductor film of the diode can be effectively serve as a rectifier element.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Fukuoka, Masahiko Hayakawa, Hideaki Shishido
  • Patent number: 8749930
    Abstract: It is an object to provide a protection circuit and a semiconductor device to which a countermeasure against ESD is applied. The protection circuit includes a signal line electrically connected to an integrated circuit; a first diode provided between the signal line and a first power supply line; a second diode provided in parallel to the first diode; and a third diode provided between the first power supply line and a second power supply line. The first diode is a diode formed by diode-connecting a transistor, and the second diode is a diode having a PIN junction or a PN junction. The protection circuit is particularly effective when applied to a semiconductor device manufactured using a thin film transistor.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Shishido, Osamu Fukuoka
  • Patent number: 8368145
    Abstract: A semiconductor device has a structure including the first semiconductor region 103 which is provided in the first terminal portion 100 and includes the first n-type impurity region 106, the first resistance region 107 provided at an inner periphery portion of the first n-type impurity region 106 in a plane view, and the first p-type impurity region 108 provided at an inner periphery portion of the first resistance region 107 in the plane view, and the second semiconductor region 104 which is provided in the second terminal portion 101 and includes the second p-type impurity region 109, the second resistance region 110 provided at an inner periphery portion of the second p-type impurity region 109 in the plane view, and the second n-type impurity region 111 provided at an inner periphery portion of the second resistance region 110 in the plane view.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: February 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Fukuoka, Masahiko Hayakawa, Hideaki Shishido
  • Patent number: 8363365
    Abstract: The resistance of an integrated circuit against ESD (electrostatic discharge) is improved without disturbing improvement of the performance and reduction of size of the integrated circuit. A protection circuit is interposed between an input and output terminals. When ESD is generated, the input and output terminals are short-circuited by the protection circuit, so that overvoltage application to the circuit is prevented. The circuit is electrically connected to the input and output terminals by a connection wiring. The circuit has a plurality of electrical connection portions between the circuit and the connection wiring, and the connection wiring is formed such that the wiring resistance between the input or output terminal and each of the connection portions is the same. Accordingly, if ESD is generated, voltage application on only one of the connection portions is prevented, whereby the possibility that the circuit will be broken by ESD is decreased.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: January 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Fukuoka, Hideaki Shishido
  • Publication number: 20120211749
    Abstract: To improve the performance of a protection circuit including a diode formed using a semiconductor film. A protection circuit is inserted between two input/output terminals. The protection circuit includes a diode which is formed over an insulating surface and is formed using a semiconductor film. Contact holes for connecting an n-type impurity region and a p-type impurity region of the diode to a first conductive film in the protection circuit are distributed over the entire impurity regions. Further, contact holes for connecting the first conductive film and a second conductive film in the protection circuit are dispersively formed over the semiconductor film. By forming the contact holes in this manner, wiring resistance between the diode and a terminal can be reduced and the entire semiconductor film of the diode can be effectively serve as a rectifier element.
    Type: Application
    Filed: May 2, 2012
    Publication date: August 23, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Osamu FUKUOKA, Masahiko HAYAKAWA, Hideaki SHISHIDO
  • Patent number: 8174047
    Abstract: To improve the performance of a protection circuit including a diode formed using a semiconductor film. A protection circuit is inserted between two input/output terminals. The protection circuit includes a diode which is formed over an insulating surface and is formed using a semiconductor film. Contact holes for connecting an n-type impurity region and a p-type impurity region of the diode to a first conductive film in the protection circuit are distributed over the entire impurity regions. Further, contact holes for connecting the first conductive film and a second conductive film in the protection circuit are dispersively formed over the semiconductor film. By forming the contact holes in this manner wiring resistance between the diode and a terminal can be reduced and the entire semiconductor film of the diode can be effectively serve as a rectifier element.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: May 8, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Fukuoka, Masahiko Hayakawa, Hideaki Shishido
  • Publication number: 20100202090
    Abstract: It is an object to provide a protection circuit and a semiconductor device to which a countermeasure against ESD is applied. The protection circuit includes a signal line electrically connected to an integrated circuit; a first diode provided between the signal line and a first power supply line; a second diode provided in parallel to the first diode; and a third diode provided between the first power supply line and a second power supply line. The first diode is a diode formed by diode-connecting a transistor, and the second diode is a diode having a PIN junction or a PN junction. The protection circuit is particularly effective when applied to a semiconductor device manufactured using a thin film transistor.
    Type: Application
    Filed: January 26, 2010
    Publication date: August 12, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hideaki SHISHIDO, Osamu FUKUOKA
  • Publication number: 20100006848
    Abstract: To improve the performance of a protection circuit including a diode formed using a semiconductor film. A protection circuit is inserted between two input/output terminals. The protection circuit includes a diode which is formed over an insulating surface and is formed using a semiconductor film. Contact holes for connecting an n-type impurity region and a p-type impurity region of the diode to a first conductive film in the protection circuit are distributed over the entire impurity regions. Further, contact holes for connecting the first conductive film and a second conductive film in the protection circuit are dispersively formed over the semiconductor film. By forming the contact holes in this manner wiring resistance between the diode and a terminal can be reduced and the entire semiconductor film of the diode can be effectively serve as a rectifier element.
    Type: Application
    Filed: July 1, 2009
    Publication date: January 14, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Osamu FUKUOKA, Masahiko HAYAKAWA, Hideaki SHISHIDO
  • Publication number: 20090321869
    Abstract: A semiconductor device has a structure including the first semiconductor region 103 which is provided in the first terminal portion 100 and includes the first n-type impurity region 106, the first resistance region 107 provided at an inner periphery portion of the first n-type impurity region 106 in a plane view, and the first p-type impurity region 108 provided at an inner periphery portion of the first resistance region 107 in the plane view, and the second semiconductor region 104 which is provided in the second terminal portion 101 and includes the second p-type impurity region 109, the second resistance region 110 provided at an inner periphery portion of the second p-type impurity region 109 in the plane view, and the second n-type impurity region 111 provided at an inner periphery portion of the second resistance region 110 in the plane view.
    Type: Application
    Filed: June 5, 2009
    Publication date: December 31, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Osamu FUKUOKA, Masahiko HAYAKAWA, Hideaki SHISHIDO
  • Publication number: 20090310265
    Abstract: The resistance of an integrated circuit against ESD (electrostatic discharge) is improved without disturbing improvement of the performance and reduction of size of the integrated circuit. A protection circuit is interposed between an input and output terminals. When ESD is generated, the input and output terminals are short-circuited by the protection circuit, so that overvoltage application to the circuit is prevented. The circuit is electrically connected to the input and output terminals by a connection wiring. The circuit has a plurality of electrical connection portions between the circuit and the connection wiring, and the connection wiring is formed such that the wiring resistance between the input or output terminal and each of the connection portions is the same. Accordingly, if ESD is generated, voltage application on only one of the connection portions is prevented, whereby the possibility that the circuit will be broken by ESD is decreased.
    Type: Application
    Filed: June 4, 2009
    Publication date: December 17, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Osamu FUKUOKA, Hideaki Shishido
  • Patent number: 5132072
    Abstract: A molding method of ceramic body comprising the following steps of:preparing a ceramic slurry by adding, to ceramic raw material powders, a solvent, organic dispersant and caking agent and mixing them altogether; casting said ceramic slurry into a mold; cooling it to a temperature lower than the melting point of said caking agent; and taking it out of the mold.This molding method is capable of dissolving cracking generation during releasing the ceramic body from a mold, facilitating machining, decreasing the binder amount of organic compounds, diminishing a firing shrinkage and obtaining a higher dimension accuracy.
    Type: Grant
    Filed: January 29, 1991
    Date of Patent: July 21, 1992
    Assignee: Kyocera Corporation
    Inventors: Osamu Fukuoka, Tatsumi Maeda, Toshiyuki Akamatsu, Kazuto Matsukami