Abstract: An image forming apparatus includes: an image carrier that rotates; and a charging member that is provided opposingly to the image carrier, and that charges a surface of the image carrier, wherein a discharge inhibitor that suppresses a discharge in an axial end portion is interposed in a portion where the charging member is opposed to the image carrier.

Abstract: The present invention provides a cleaning device including a cleaning member that cleans a surface of a rotating cylindrical element to be cleaned, and whose length in a longitudinal direction is longer than a length of the maximum operating region of the element to be cleaned, a length of a contact part of the cleaning member at which the cleaning member contacts with the element to be cleaned being shorter than the length in the longitudinal direction of the cleaning member, and the contact part being moved in the longitudinal direction of the element to be cleaned.

Abstract: An image forming apparatus includes a photoreceptor having on a surface thereof a photosensitive layer, in which an electrostatic latent image is formed, a contact charging roll applied with a bias containing a direct current component having superimposed thereon an alternating current component, the contact charging roll charging the photoreceptor to a predetermined potential, a film thickness detecting unit detecting a film thickness of the photosensitive layer of the photoreceptor, an environment detecting unit detecting environment, and a contact area changing unit changing a contact area between the contact charging roll and the photoreceptor based on detected results of the film thickness detecting unit and the environment detecting unit.

Abstract: An image formation apparatus includes: a photoconductor that has a photoconductive layer having a surface on which an electrostatic latent image is formed; a charging roll to which a bias with an AC component superposed on a DC component is applied for charging the photoconductor at a predetermined potential; a film thickness detector that detects a film thickness of the photoconductive layer of the photoconductor without applying the AC component; an environment measuring section that measures at least one of ambient temperature and humidity; an AC component setting section that sets a value of the AC component of the bias based on detection results of the film thickness detector and the environment measuring section; and a charging controller that controls at least one of voltage and current applied to the charging roll based on the value of the AC component set by the AC component setting section.

Abstract: An image forming device has a charging roller including a shaft which is rotatably supported and a cleaning roller that abuts the charging roller. The cleaning roller includes a shaft that is rotatably supported and a porous elastic layer being provided around the shaft. The image forming device satisfies the relation T×?/100>(R1+R2)?L>B>0, where L [mm] is a separation distance of axial centers of both end portions of the shaft of the cleaning roller and the shaft of the charging roller, R1 [mm] is a radius of the charging roller, T [mm] is a thickness of the porous elastic layer, R2 [mm] is a radius of the cleaning roller, B [mm] is a flexure amount of an axial direction central portion of the shaft of the cleaning roller, and ? [%] is a maximum allowable compression rate in accordance with a stress-flexure curve.

Abstract: An image forming device includes a charging roller that charges a body-to-be-charged by press-contacting and is rotated by the rotating body-to-be-charged, a first receiving portion that supports a supporting portion provided at the charging roller, and causes the charging roller to press-contact the body-to-be-charged, a cleaning member that press-contacts a surface of the charging roller and cleans the charging roller, and a second receiving portion that supports a supporting portion provided at the cleaning member, and causes the cleaning member to press-contact the charging roller. At least one of the first and second receiving portions imparts a degree of freedom at a first receiving portion side to the supporting portion of the charging roller in a direction of press-contacting the body-to-be-charged, and imparts a degree of freedom at a second receiving portion side to the supporting portion of the cleaning member in a direction of press-contacting the charging roller.

Abstract: The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory 120 separate from main data stored in main memory 110. In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit 300 corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.

Abstract: A nonvolatile memory cell in the form of an SRAM is composed of ferroelectric capacitors and transistors for amplification. The memory cell comprises a first capacitor (FC1) connected between a first terminal (ND1) and a common terminal (CP). A second capacitor (FC2) is connected between a second terminal (ND2) and the common terminal. A first transistor (N1) has a current path connected between the first terminal and a reference terminal (GND) and has a control terminal connected to the second terminal. A second transistor (N2) has a current path connected between the second terminal and the reference terminal and has a control terminal connected to the first terminal.

Abstract: The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory 120 separate from main data stored in main memory 110. In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit 300 corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.

Abstract: A nonvolatile memory cell in the form of an SRAM is composed of ferroelectric capacitors and transistors for amplification. The memory cell comprises a first capacitor (FC1) connected between a first terminal (ND1) and a common terminal (CP). A second capacitor (FC2) is connected between a second terminal (ND2) and the common terminal. A first transistor (N1) has a current path connected between the first terminal and a reference terminal (GND) and has a control terminal connected to the second terminal. A second transistor (N2) has a current path connected between the second terminal and the reference terminal and has a control terminal connected to the first terminal.

Abstract: A nonvolatile memory cell in the form of an SRAM is composed of ferroelectric capacitors and transistors for amplification. The memory cell comprises a first capacitor (FC1) connected between a first terminal (ND1) and a common terminal (CP). A second capacitor (FC2) is connected between a second terminal (ND2) and the common terminal. A first transistor (N1) has a current path connected between the first terminal and a reference terminal (GND) and has a control terminal connected to the second terminal. A second transistor (N2) has a current path connected between the second terminal and the reference terminal and has a control terminal connected to the first terminal.

Abstract: A semiconductor circuit which can restrain increase in manufacturing cost and layout area to a minimum level and can realize high speed and low power consumption. Bias voltages with different levels are generated corresponding to a mode control signal by a bias voltage supply circuit comprising PMOS transistors P2 and P3 which have different voltages applied to the respective sources and the mode control signal input to the gates. The generated bias voltages are supplied to the n-wells of PMOS transistors. During operation, a bias voltage that is almost the same as the operation voltage is applied to the n-wells of PMOS transistors. During standby, a bias voltage higher than the operation voltage is supplied to the aforementioned n-wells of PMOS transistors. In this way, the driving currents of the transistors can be kept at a high level during operation, while leakage currents of the transistors can be restrained during standby. Consequently, high speed and low power consumption can be realized.

Abstract: A nonvolatile memory cell in the form of an SRAM is composed of ferroelectric capacitors and transistors for amplification. The memory cell comprises a first capacitor (FC1) connected between a first terminal (ND1) and a common terminal (CP). A second capacitor (FC2) is connected between a second terminal (ND2) and the common terminal. A first transistor (N1) has a current path connected between the first terminal and a reference terminal (GND) and has a control terminal connected to the second terminal. A second transistor (N2) has a current path connected between the second terminal and the reference terminal and has a control terminal connected to the first terminal.

Abstract: The objective of this invention is to provide a type of semiconductor integrated circuit which can lessen solution in the circuit area to the minimum necessary level, and can lessen the leakage current in the standby state so as to cut the power consumption, and which allows Iddq test to determine whether it is passed or defective. Logic circuit 10 composed of low threshold voltage transistors and switching circuit 20 composed of transistors having the standard threshold voltage are set. In the operation, the switching circuit is turned ON, and a driving current is fed to logic circuit 10. On the other hand, in the standby mode, the switching circuit is turned OFF, and the path of the leakage current is cut off to lessen generation of the leakage current. In the case of Iddq test, different bulk bias voltages are applied to the channel regions of PMOS transistors and NMOS transistors from an IC tester through pads P1 and P2.

Abstract: The objective of the invention is to provide a type of semiconductor memory device equipped with an error correction circuit 200 characterized by the fact that it can perform correction of errors in stored data without increasing the circuit size and power consumption, and without decreasing operating speed. An error correction code EC corresponds to data stored in sub-memory 120 separate from main data stored in main memory 110. In read mode, the main data and error correction code are read from the main memory and sub-memory, respectively. On the basis of these data, the error correction code is generated for correcting errors in the read data. Error correction circuit 300 corrects errors in the main data. By storing the error correction code in a sub-memory different from the main memory and selecting the appropriate layout of the main memory and sub-memory, it is possible to increase the reading speed of the error correction code and to suppress time delays caused by error correction.

Abstract: The objective of this invention is to provide a type of semiconductor integrated circuit which can lessen solution in the circuit area to the minimum necessary level, and can lessen the leakage current in the standby state so as to cut the power consumption, and which allows Iddq test to determine whether it is passed or defective. Logic circuit 10 composed of low threshold voltage transistors and switching circuit 20 composed of transistors having the standard threshold voltage are set. In the operation, the switching circuit is turned ON, and a driving current is fed to logic circuit 10. On the other hand, in the standby mode, the switching circuit is turned OFF, and the path of the leakage current is cut off to lessen generation of the leakage current. In the case of Iddq test, different bulk bias voltages are applied to the channel regions of PMOS transistors and NMOS transistors from an IC tester through pads P1 and P2.

Abstract: A semiconductor circuit which can restrain increase in manufacturing cost and layout area to a minimum level and can realize high speed and low power consumption. Bias voltages with different levels are generated corresponding to a mode control signal by a bias voltage supply circuit comprising PMOS transistors P2 and P3 which have different voltages applied to the respective sources and the mode control signal input to the [respective] gates. The generated bias voltages are supplied to the n-wells of PMOS transistors. During operation, a bias voltage that is almost the same as the operation voltage is applied to the n-wells of PMOS transistors. During standby, a bias voltage higher than the operation voltage is supplied to the aforementioned n-wells of PMOS transistors. In this way, the driving currents of the transistors can be kept at a high level during operation, while leakage currents of the transistors can be restrained during standby.

Abstract: There is described an image forming apparatus, wherein a visible image retained on an intermediate transfer belt is collectively transferred to recording material by means of a collective transfer device including a transfer roller and a back-up roller. The recording material that has passed through a transfer nipping region is guided by means of a recording material guide member. In such an image forming apparatus, the intermediate transfer belt is set at an angle of 50.degree. or less relative to the reference line passing through the exit of the transfer nipping region between the transfer roller and the back-up roller among normals orthogonal to a line passing through the center shafts of the transfer roller and the back-up roller, in the area downstream from the transfer nipping region, and the recording material guide member is provided downward at an angle of 5.degree. to 20.degree. relative to the reference line L.

Abstract: A transfer apparatus for electrostatically transferring a toner image of a given polarity supported on an image support to a recording medium includes a transfer roll and a cleaning member. The transfer roll comes in rolling contact with the image support in synchronization therewith and has a transfer electric field of an opposite polarity to toner formed in a gap between the transfer roll and the image support. The cleaning member abuts the transfer roll to remove residues on the transfer roll. A charged property of a contact surface portion between the cleaning member and the transfer roll is set so that a charge polarity on a surface of the transfer roll produced as the cleaning member abuts the transfer roll becomes the same as a toner polarity on the image support.

Abstract: A transfer apparatus is provided which is capable of effectively preventing a defect in transference caused from a gap between a transfer member and an intermediate transfer belt to form an excellent image free from an image defect such as whitening. The transfer apparatus for an image forming apparatus for primarily transferring a toner image formed on an image holding member to an intermediate transfer belt and then secondarily transferring the image, which has been primarily transferred onto the intermediate transfer belt, to a transfer member, includes a transfer unit for secondarily transferring the image having a transfer roll separably disposed on the surface of the intermediate transfer belt, which holds the toner image, and an opposite roll disposed to be in contact with the inner surface of the intermediate transfer belt at a position at which the opposite roll is opposite to the transfer roll.