Abstract: A consistency ensuring system has at least one main memory and a plurality of processors each having a corresponding instruction cache memory and operand cache memory. Each of the plurality of processors includes a flush address array device, an address converting device, a signal generating device and a flush address array invalidating device. The flush address array device maintains a copy of an address array to be looked up for invalidating a block of data in the cache memories of the corresponding processor in response to storing a corresponding block of data into the main memory from another processor. The address converting device converts a virtual address to a real address and updates a page table word after address conversion and storage of the updated page table word in the main memory but not in the corresponding cache memories. The signal generating device generates a page table word store notice signal when the address converting device stores the updated page table into the main memory.

Abstract: A multilevel cache memory system has a pseudo-error indicating flag for storing a first logic state when the system is in a normal error checking mode and a second logic state when the system is in a pseudo-error verification mode. First logic gate circuits, associated respectively with the levels of the cache memory, are arranged to be disabled in response to the first logic state and enabled in response to the second logic state. Register stages corresponding in number to the levels of the cache memory stores level-invalidating data. Second logic gate circuits are associated respectively with the register stages for sequentially activating one of the first logic gate circuits in accordance with logic states of the register stages when the first logic gate circuits are enabled. Second flags are associated respectively with the first logic gate circuits to give an error indication in response to the activated first logic gate circuits.