Patents by Inventor Osamu Hidaka
Osamu Hidaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050118795Abstract: A semiconductor memory device includes a semiconductor substrate having a first region and a second region, a transistor placed in the first region of the semiconductor substrate, a first insulating film formed on the semiconductor substrate in the first and second regions and on the transistor, a first ferroelectric capacitor formed on the first insulating film in the first region and electrically connected to the transistor, a hydrogen barrier film formed above the first ferroelectric capacitor and above the first insulating film in the first and second regions, a first contact penetrating the hydrogen barrier film in the first region and electrically connected to the first ferroelectric capacitor, and a second contact which penetrates the hydrogen barrier film in the second region and which is in a floating state.Type: ApplicationFiled: July 8, 2004Publication date: June 2, 2005Inventors: Osamu Hidaka, Iwao Kunishima, Hiroyuki Kanaya
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Publication number: 20040163233Abstract: A fabrication process for ferroelectric capacitors includes forming openings 23, 30, in the device, into which electrically conductive material 28, 37 can be inserted to form electrical connections within the device. The surface of each opening is coated with a layer 24, 34 of getter material which absorbs contaminants 25, 31, 33 formed during the opening process. This means that in subsequent processing steps the contaminants do not vagabond towards the ferroelectric layers 7 of the device where they might otherwise cause damage, for example during a subsequent crystallisation stage.Type: ApplicationFiled: February 26, 2003Publication date: August 26, 2004Inventors: Stefan Gernhardt, Osamu Hidaka, Jenny Lian, Rainer Bruchhaus, Andreas Hilliger, Nicolas Nagel
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Patent number: 6750093Abstract: A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a fist hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.Type: GrantFiled: December 6, 2002Date of Patent: June 15, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kanaya, Osamu Hidaka, Kumi Okuwada, Hiroshi Mochizuki
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Publication number: 20040084701Abstract: A semiconductor device having a semiconductor substrate; an insulating film formed on said semiconductor substrate; a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode which are stacked sequentially on the insulating film; a first hydrogen barrier film; a first inter-layer insulating film covering said ferroelectric capacitor; and a second inter-layer insulating film stacked on the first inter-layer insulating film, the first hydrogen barrier film being interposed between the first and second interlayer insulating films is proposed.Type: ApplicationFiled: June 25, 2003Publication date: May 6, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kanaya, Toyota Morimoto, Osamu Hidaka, Yoshinori Kumura, Iwao Kunishima, Tsuyoshi Iwamoto
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Patent number: 6699726Abstract: The semiconductor device is constituted in such a manner that a switching transistor having a drain region and a source region which are comprised of an impurity-diffused region is formed in the surface layer portion of a semiconductor substrate. On the semiconductor substrate containing the transistor, a first insulation film is formed, and, at the upper layer side of the first insulation film, a capacitor is formed. The capacitor is comprised of a lower electrode, an inter-electrode insulation film comprising one of ferroelectric and high-permittivity dielectric, and an upper electrode. Before the inter-electrode insulation film is formed, a second insulation film is formed so as to cover the side face portion of the inter-electrode insulation film, the second insulation film protecting the side face portion of the inter-electrode insulation film.Type: GrantFiled: January 3, 2003Date of Patent: March 2, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Hidaka, Sumito Ootsuki, Hiroshi Mochizuki, Hiroyuki Kanaya, Kumi Okuwada, Tomio Katata, Norihisa Arai, Hiroyuki Takenaka
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Patent number: 6611014Abstract: A semiconductor device having a semiconductor substrate; an insulating film formed on said semiconductor substrate; a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode which are stacked sequentially on the insulating film; a first hydrogen barrier film; a first inter-layer insulating film covering said ferroelectric capacitor; and a second inter-layer insulating film stacked on the first inter-layer insulating film, the first hydrogen barrier film being interposed between the first and second interlayer insulating films is proposed.Type: GrantFiled: May 12, 2000Date of Patent: August 26, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kanaya, Toyota Morimoto, Osamu Hidaka, Yoshinori Kumura, Iwao Kunishima, Tsuyoshi Iwamoto
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Publication number: 20030134464Abstract: The semiconductor device is constituted in such a manner that a switching transistor having a drain region and a source region which are comprised of an impurity-diffused region is formed in the surface layer portion of a semiconductor substrate. On the semiconductor substrate containing the transistor, a first insulation film is formed, and, at the upper layer side of the first insulation film, a capacitor is formed. The capacitor is comprised of a lower electrode, an inter-electrode insulation film comprising one of ferroelectric and high-permittivity dielectric, and an upper electrode. Before the inter-electrode insulation film is formed, a second insulation film is formed so as to cover the side face portion of the inter-electrode insulation film, the second insulation film protecting the side face portion of the inter-electrode insulation film.Type: ApplicationFiled: January 3, 2003Publication date: July 17, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Osamu Hidaka, Sumito Ootsuki, Hiroshi Mochizuki, Hiroyuki Kanaya, Kumi Okuwada, Tomio Katata, Norihisa Arai, Hiroyuki Takenaka
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Publication number: 20030092235Abstract: A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a fist hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.Type: ApplicationFiled: December 6, 2002Publication date: May 15, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kanaya, Osamu Hidaka, Kumi Okuwada, Hiroshi Mochizuki
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Patent number: 6521927Abstract: The semiconductor device is constituted in such a manner that a switching transistor having a drain region and a source region which are comprised of an impurity-diffused region is formed in the surface layer portion of a semiconductor substrate. On the semiconductor substrate containing the transistor, a first insulation film is formed, and, at the upper layer side of the first insulation film, a capacitor is formed. The capacitor is comprised of a lower electrode, an inter-electrode insulation film comprising one of ferroelectric and high-permittivity dielectric, and an upper electrode. Before the inter-electrode insulation film is formed, a second insulation film is formed so as to cover the side face portion of the inter-electrode insulation film, the second insulation film protecting the side face portion of the inter-electrode insulation film.Type: GrantFiled: June 23, 1998Date of Patent: February 18, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Hidaka, Sumito Ootsuki, Hiroshi Mochizuki, Hiroyuki Kanaya, Kumi Okuwada, Tomio Katata, Norihisa Arai, Hiroyuki Takenaka
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Patent number: 6511877Abstract: A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a fist hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.Type: GrantFiled: August 6, 2001Date of Patent: January 28, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kanaya, Osamu Hidaka, Kumi Okuwada, Hiroshi Mochizuki
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Publication number: 20020040988Abstract: The semiconductor device is constituted in such a manner that a switching transistor having a drain region and a source region which are comprised of an impurity-diffused region is formed in the surface layer portion of a semiconductor substrate. On the semiconductor substrate containing the transistor, a first insulation film is formed, and, at the upper layer side of the first insulation film, a capacitor is formed. The capacitor is comprised of a lower electrode, an inter-electrode insulation film comprising one of ferroelectric and high-permittivity dielectric, and an upper electrode. Before the inter-electrode insulation film is formed, a second insulation film is formed so as to cover the side face portion of the inter-electrode insulation film, the second insulation film protecting the side face portion of the inter-electrode insulation film.Type: ApplicationFiled: June 23, 1998Publication date: April 11, 2002Inventors: OSAMU HIDAKA, SUMITO OOTSUKI, HIROSHI MOCHIZUKI, HIROYUKI KANAYA, KUMI OKUWADA, TOMIO KATATA, NORIHISA ARAI, HIROYUKI TAKENAKA
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Publication number: 20010051414Abstract: A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a fist hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.Type: ApplicationFiled: August 6, 2001Publication date: December 13, 2001Inventors: Hiroyuki Kanaya, Osamu Hidaka, Kumi Okuwada, Hiroshi Mochizuki
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Patent number: 6303958Abstract: A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a first hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.Type: GrantFiled: June 11, 1998Date of Patent: October 16, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kanaya, Osamu Hidaka, Kumi Okuwada, Hiroshi Mochizuki
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Patent number: 6190957Abstract: A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.Type: GrantFiled: June 2, 1999Date of Patent: February 20, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Mochizuki, Kumi Okuwada, Hiroyuki Kanaya, Osamu Hidaka, Susumu Shuto, Iwao Kunishima
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Patent number: 5990507Abstract: A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.Type: GrantFiled: July 8, 1997Date of Patent: November 23, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Mochizuki, Kumi Okuwada, Hiroyuki Kanaya, Osamu Hidaka, Susumu Shuto, Iwao Kunishima
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Patent number: 5124620Abstract: When a welding teaching program employing a plurality of robots is completed, if a robot does not operate properly it may be preferably to make the robot retreat and operate in accordance with a different teaching program, urgently and at an optional timing. In the invention, when the operation of a program being executed is suspended, the program addresses are memorized and a different prestored teaching program is executed. Upon the termination of the different teaching program, the execution of the suspended program is resumed, referring to the memorized addresses.Type: GrantFiled: August 21, 1990Date of Patent: June 23, 1992Assignee: Kabushiki Kaisha Yaskawa Denki SeisakushoInventors: Toshiyuki Kurebayashi, Satoshi Kuranaga, Tatsuya Fukunaga, Osamu Hidaka