Abstract: A semiconductor memory includes: a non-volatile memory cell including a floating gate and a memory transistor; a state machine that generates a normal program signal for performing a normal program operation and a verify signal for performing a verify operation and generates a soft program signal for performing a soft program operation when detecting a fail in the verify operation after the normal program operation, whether a threshold voltage of the memory transistor reaches a value being checked in the verify operation; a voltage generating circuit that generates a normal program voltage and a verify voltage based on the normal program signal and the verify signal and generates a soft program voltage based on the soft program signal; and a determination circuit that detects a pass when the threshold voltage reaches the value and detects the fail when the threshold voltage does not reach the value.

Abstract: A semiconductor memory device including: a memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells arranged in portions where the plurality of word lines and the plurality of bit lines intersect with each other; a plurality of data bus lines connected to the plurality of bit lines; a plurality of sense amplifiers individually connected to the plurality of data bus lines and configured for detecting memory data stored in corresponding memory cells based on values of currents that are generated in the individual data bus lines in accordance with the memory data.

Abstract: A semiconductor memory includes: a non-volatile memory cell including a floating gate and a memory transistor; a state machine that generates a normal program signal for performing a normal program operation and a verify signal for performing a verify operation and generates a soft program signal for performing a soft program operation when detecting a fail in the verify operation after the normal program operation, whether a threshold voltage of the memory transistor reaches a value being checked in the verify operation; a voltage generating circuit that generates a normal program voltage and a verify voltage based on the normal program signal and the verify signal and generates a soft program voltage based on the soft program signal; and a determination circuit that detects a pass when the threshold voltage reaches the value and detects the fail when the threshold voltage does not reach the value.

Abstract: When different word lines are accessed sequentially, to perform access operations in parallel, a word decoder overlaps a part of activation periods of those word lines. That is, a nonvolatile semiconductor memory is capable of pipeline processing for performing access operations in parallel. All the combinations of bit lines and source lines that are connected to the drains and the sources of nonvolatile memory cells are different from each other. Therefore, even when plural word lines are activated to perform plural read operations in parallel, a memory cell current is allowed to flow only between the drain and the source of a nonvolatile memory cell concerned. As a result, random access in which desired nonvolatile memory cells are accessed sequentially is enabled in a nonvolatile semiconductor memory having a pipeline function for performing plural read operations in parallel.

Abstract: A charge loss restoration method detects a memory cell having a tendency of a charge loss within a memory cell array of an electrically writable and erasable nonvolatile semiconductor memory device, using a charge loss detecting reference cell having a threshold value set between a threshold value of a read reference cell and a threshold value of a write verify reference cell, where the threshold value of the write verify reference cell is higher than the threshold value of the read reference cell, and restores the memory cell having the tendency of the charge loss by making an additional write thereto.

Abstract: A semiconductor memory device including: a memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells arranged in portions where the plurality of word lines and the plurality of bit lines intersect with each other; a plurality of data bus lines connected to the plurality of bit lines; a plurality of sense amplifiers individually connected to the plurality of data bus lines and configured for detecting memory data stored in corresponding memory cells based on values of currents that are generated in the individual data bus lines in accordance with the memory data.

Abstract: A charge loss restoration method detects a memory cell having a tendency of a charge loss within a memory cell array of an electrically writable and erasable nonvolatile semiconductor memory device, using a charge loss detecting reference cell having a threshold value set between a threshold value of a read reference cell and a threshold value of a write verify reference cell, where the threshold value of the write verify reference cell is higher than the threshold value of the read reference cell, and restores the memory cell having the tendency of the charge loss by making an additional write thereto.

Abstract: A nonvolatile semiconductor memory is capable of dual and triple operation with a small chip size. A plurality of sectors is formed. Each sector has nonvolatile memory cells, local bit lines connected to these memory cells, and switch circuits. Write global bit lines and read global bit lines are each wired commonly to the sectors. The write global bit lines transfer write data to the memory cells or verify data from the memory cells. The read global bit lines transfer read data from the memory cells. The switch circuits connect the local bit lines to the write global bit lines or the read global bit lines in accordance with the operation modes. Consequently, it is possible to execute read operation while executing a write sequence or an erase sequence. That is, dual operation can be executed.

Abstract: A redundancy substitution method for memory cells within an electrically writable and erasable semiconductor memory device, includes detecting a memory cell having a tendency of a charge loss and/or a charge gain, by use of a charge loss detecting reference cell and/or a charge gain detecting reference cell. The charge loss detecting reference cell has a threshold value set between a threshold value of a read reference cell and a threshold value of a write verify reference cell that is higher than that of the read reference cell, and the charge gain detecting reference cell has a threshold value set between the threshold value of the read reference cell and a threshold value of an erase verify reference cell that is lower than that of the read reference cell. The method subjects a memory cell whose tendency of the charge loss and/or the charge gain is detected to a redundancy substitution.

Abstract: When different word lines are accessed sequentially, to perform access operations in parallel, a word decoder overlaps a part of activation periods of those word lines. That is, a nonvolatile semiconductor memory is capable of pipeline processing for performing access operations in parallel. All the combinations of bit lines and source lines that are connected to the drains and the sources of nonvolatile memory cells are different from each other. Therefore, even when plural word lines are activated to perform plural read operations in parallel, a memory cell current is allowed to flow only between the drain and the source of a nonvolatile memory cell concerned. As a result, random access in which desired nonvolatile memory cells are accessed sequentially is enabled in a nonvolatile semiconductor memory having a pipeline function for performing plural read operations in parallel.

Abstract: An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patterns formed in a second interlayer insulation film separated from the first interlayer insulation film by a via-insulation film, such that the third and fourth conductor patterns extend in the second layer interlayer insulation film continuously in a mutually opposing relationship as a part of the comb-shaped capacitor pattern, wherein there is formed a fifth conductor pattern extending in the via-insulation film continuously in correspondence to the first and third conductor patterns so as to connect the first and third conductor patterns continuously, and wherein there is formed a sixth conductor pattern extending in the via-insulation film continuously in correspondence to the second and fourth conductor patterns so as to connect the second and f

Abstract: A redundancy substitution method for memory cells within an electrically writable and erasable semiconductor memory device, includes detecting a memory cell having a tendency of a charge loss and/or a charge gain, by use of a charge loss detecting reference cell and/or a charge gain detecting reference cell. The charge loss detecting reference cell has a threshold value set between a threshold value of a read reference cell and a threshold value of a write verify reference cell that is higher than that of the read reference cell, and the charge gain detecting reference cell has a threshold value set between the threshold value of the read reference cell and a threshold value of an erase verify reference cell that is lower than that of the read reference cell. The method subjects a memory cell whose tendency of the charge loss and/or the charge gain is detected to a redundancy substitution.

Abstract: An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patterns formed in a second interlayer insulation film separated from the first interlayer insulation film by a via-insulation film, such that the third and fourth conductor patterns extend in the second layer interlayer insulation film continuously in a mutually opposing relationship as a part of the comb-shaped capacitor pattern, wherein there is formed a fifth conductor pattern extending in the via-insulation film continuously in correspondence to the first and third conductor patterns so as to connect the first and third conductor patterns continuously, and wherein there is formed a sixth conductor pattern extending in the via-insulation film continuously in correspondence to the second and fourth conductor patterns so as to connect the second and f

Abstract: An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patterns formed in a second interlayer insulation film separated from the first interlayer insulation film by a via-insulation film, such that the third and fourth conductor patterns extend in the second layer interlayer insulation film continuously in a mutually opposing relationship as a part of the comb-shaped capacitor pattern, wherein there is formed a fifth conductor pattern extending in the via-insulation film continuously in correspondence to the first and third conductor patterns so as to connect the first and third conductor patterns continuously, and wherein there is formed a sixth conductor pattern extending in the via-insulation film continuously in correspondence to the second and fourth conductor patterns so as to connect the second and f

Abstract: An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patterns formed in a second interlayer insulation film separated from the first interlayer insulation film by a via-insulation film, such that the third and fourth conductor patterns extend in the second layer interlayer insulation film continuously in a mutually opposing relationship as a part of the comb-shaped capacitor pattern, wherein there is formed a fifth conductor pattern extending in the via-insulation film continuously in correspondence to the first and third conductor patterns so as to connect the first and third conductor patterns continuously, and wherein there is formed a sixth conductor pattern extending in the via-insulation film continuously in correspondence to the second and fourth conductor patterns so as to connect the second and f

Abstract: A nonvolatile semiconductor memory is capable of dual and triple operation with a small chip size. A plurality of sectors is formed. Each sector has nonvolatile memory cells, local bit lines connected to these memory cells, and switch circuits. Write global bit lines and read global bit lines are each wired commonly to the sectors. The write global bit lines transfer write data to the memory cells or verify data from the memory cells. The read global bit lines transfer read data from the memory cells. The switch circuits connect the local bit lines to the write global bit lines or the read global bit lines in accordance with the operation modes. Consequently, it is possible to execute read operation while executing a write sequence or an erase sequence. That is, dual operation can be executed.

Abstract: A nonvolatile semiconductor memory device includes a virtual-ground memory array which includes a plurality of nonvolatile memory cells and sub-bit lines connected to the nonvolatile memory cells, first and second selection lines, first and second selection transistors which become conductive in response to activation of the first selection line, a third selection transistor which become conductive in response to activation of the second selection line, a first main bit line which is coupled to and supplies a drain potential to a sub-bit line situated on a drain side of a selected memory cell through the first selection transistor, a second main bit line which is coupled to and supplies a source potential to a sub-bit line situated on a source side of the selected memory cell through one of the second selection transistor and the third selection transistor, and a third main bit line which is coupled to a sub-bit line adjacent to the sub-bit line situated on the drain side of the selected memory cell through a

Abstract: A nonvolatile semiconductor memory device includes a virtual-ground memory array which includes a plurality of nonvolatile memory cells and sub-bit lines connected to the nonvolatile memory cells, first and second selection lines, first and second selection transistors which become conductive in response to activation of the first selection line, a third selection transistor which become conductive in response to activation of the second selection line, a first main bit line which is coupled to and supplies a drain potential to a sub-bit line situated on a drain side of a selected memory cell through the first selection transistor, a second main bit line which is coupled to and supplies a source potential to a sub-bit line situated on a source side of the selected memory cell through one of the second selection transistor and the third selection transistor, and a third main bit line which is coupled to a sub-bit line adjacent to the sub-bit line situated on the drain side of the selected memory cell through a