Patents by Inventor Osamu Kasahara

Osamu Kasahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11971644
    Abstract: Reduction of output power of light with a wavelength converted is suppressed, which is caused by a pyroelectric effect that occurs when a temperature of a wavelength conversion element including a ferroelectric substrate is changed.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: April 30, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Koji Embutsu, Ryoichi Kasahara, Osamu Tadanaga, Takeshi Umeki, Takahiro Kashiwazaki, Takushi Kazama
  • Patent number: 11958100
    Abstract: The wire fed or pulled back from the reel by the feeding unit can be properly restricted. The invention relates to a binding machine (2) having a feeding unit (16) for feeding out a wire (3) from a reel (12) provided in a housing unit (11). With respect to the entering route (81) of the wire (3) when the wire (3) drawn out from the reel (12) by the feeding unit (16) is guided to the feeding unit (83), the first restriction unit (83) that restricts the drawing portion (3a) of the wire (3) disposed between the reel (12) and the feeding unit (16) from being deviating from the entering route (81) is provided inside the housing unit (11).
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 16, 2024
    Assignee: Max Co., Ltd.
    Inventors: Akira Kasahara, Osamu Itagaki, Ichiro Kusakari, Takeshi Morijiri
  • Patent number: 11946267
    Abstract: A binding machine includes a wire feeding unit configured to feed a wire, a curl guide configured to curl the wire fed by the wire feeding unit around an object to be bound, a binding unit including a twisting shaft provided to be rotatable around a predetermined axis, and a gripping part provided at one end side of the twisting shaft, wherein the gripping part is configured to grip the wire curled by the curl guide and the twisting shaft is configured to twist the gripped wire so as to bind the object, a binding machine main body having one end side at which the curl guide is arranged and configured to accommodate therein the wire feeding unit and the binding unit, and a setting unit provided at an opposite end side of the binding machine main body and configured to set a predetermined operation condition.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: April 2, 2024
    Assignee: Max Co., Ltd.
    Inventors: Osamu Itagaki, Akira Kasahara, Norihiro Nagai
  • Patent number: 9096928
    Abstract: Provided is a method of manufacturing a semiconductor device, including: forming a silicon oxide film on a surface of a substrate holder by repeatedly performing forming a silicon-containing layer on the surface of the substrate holder and oxidizing the silicon-containing layer; forming a thin film on a substrate by using a process gas; removing deposits attached onto the substrate holder by using a fluorine-containing gas; and reforming a silicon oxide film on the surface of the substrate holder after removal of the deposits by repeatedly performing forming a silicon-containing layer on the surface of the substrate holder and oxidizing the silicon-containing layer by using an oxygen-containing gas and a hydrogen-containing gas.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: August 4, 2015
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Ryota Sasajima, Yoshiro Hirose, Naonori Akae, Osamu Kasahara
  • Patent number: 9023429
    Abstract: A method of manufacturing a semiconductor device including: mounting a substrate on a substrate mounting member that is disposed in a reaction container; heating the substrate at a predetermined processing temperature and supplying a first gas and a second gas to the substrate to process the substrate; stopping supply of the first gas and the second gas, and supplying an inert gas into the reaction container; and unloading the substrate to outside the reaction container.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: May 5, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yuichiro Takeshima, Osamu Kasahara, Kazuyuki Toyoda, Junichi Tanabe, Katsuhiko Yamamoto, Hisashi Nomura
  • Publication number: 20140087567
    Abstract: Provided is a substrate processing apparatus including: a substrate mounting portion provided in a process chamber and capable of mounting a plurality of substrates in a circumferential direction; a rotating mechanism that rotates the substrate mounting portion at a predetermined angular velocity; dividing structures provided in a radial form from a center of a lid of the process chamber so as to divide the process chamber into a plurality of areas; and gas supply areas disposed between the adjacent dividing structures, wherein an angle between the adjacent dividing structures with one gas supply area interposed is set to an angle corresponding to the angular velocity and a period in which a portion of the substrate mounting portion passes through the gas supply area.
    Type: Application
    Filed: September 27, 2013
    Publication date: March 27, 2014
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Kazuyuki TOYODA, Osamu KASAHARA, Tetsuaki INADA, Junichi TANABE, Tatsushi UEDA
  • Patent number: 8575042
    Abstract: In a low-temperature, a silicon nitride film having a low in-film chlorine (Cl) content and a high resistance to hydrogen fluoride (HF) is formed. The formation of the silicon nitride film includes (a) supplying a monochlorosilane (SiH3Cl or MCS) gas to a substrate disposed in a processing chamber, (b) supplying a plasma-excited hydrogen-containing gas to the substrate disposed in the processing chamber, (c) supplying a plasma-excited or heat-excited nitrogen-containing gas to the substrate disposed in the processing chamber, (d) supplying at least one of a plasma-excited nitrogen gas and a plasma-excited rare gas to the substrate disposed in the processing chamber, and (e) performing a cycle including the steps (a) through (d) a predetermined number of times to form a silicon nitride film on the substrate.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: November 5, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yosuke Ota, Yoshiro Hirose, Atsushi Sano, Osamu Kasahara, Kazuyuki Okuda, Kiyohiko Maeda
  • Publication number: 20130276983
    Abstract: A plasma processing apparatus may include a process chamber configured to perform a plasma using process and contain a plurality of substrates, a support member provided in the process chamber, the substrates being laid on the same level of the support member, an injection member provided to face the support member and include a plurality of baffles, such that at least one reaction gas and a purge gas can be injected onto the substrates in an independent manner, and a driving part configured to rotate the support member or the injection member, such that the baffles of the injection member can orbit with respect to the plurality of the substrates laid on the support member. The injection member may include a plasma generator, which may be provided on at least one, configured to inject the reaction gas, of the baffles to turn the reaction gas into plasma.
    Type: Application
    Filed: January 12, 2012
    Publication date: October 24, 2013
    Applicants: HITACHI KOKUSAI ELECTRIC INC., KOOKJE ELECTRIC KOREA CO., LTD.
    Inventors: Yong Sung Park, Sung Kwang Lee, Dong Yeul Kim, Kazuyuki Toyoda, Osamu Kasahara, Tetsuaki Inada
  • Patent number: 8293646
    Abstract: A high quality interface is formed at a low oxygen-carbon density between a substrate and a thin film while preventing heat damage on the substrate and increase of thermal budget. This method includes a step of loading a wafer into a reaction furnace, a step of pretreating the wafer in the reaction furnace, a step of performing a main processing of the pretreated wafer in the reaction furnace, and a step of unloading the wafer from the reaction furnace after the main processing. Hydrogen gas is continuously supplied to the reaction furnace in the period from the end of the pretreating step to the start of the main processing and at least during vacuum-exhausting an interior of the reaction furnace.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: October 23, 2012
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Takashi Ozaki, Osamu Kasahara, Takaaki Noda, Kiyohiko Maeda, Atsushi Moriya, Minoru Sakamoto
  • Publication number: 20120220137
    Abstract: In a low-temperature, a silicon nitride film having a low in-film chlorine (Cl) content and a high resistance to hydrogen fluoride (HF) is formed. The formation of the silicon nitride film includes (a) supplying a monochlorosilane (SiH3Cl or MCS) gas to a substrate disposed in a processing chamber, (b) supplying a plasma-excited hydrogen-containing gas to the substrate disposed in the processing chamber, (c) supplying a plasma-excited or heat-excited nitrogen-containing gas to the substrate disposed in the processing chamber, (d) supplying at least one of a plasma-excited nitrogen gas and a plasma-excited rare gas to the substrate disposed in the processing chamber, and (e) performing a cycle including the steps (a) through (d) a predetermined number of times to form a silicon nitride film on the substrate.
    Type: Application
    Filed: February 27, 2012
    Publication date: August 30, 2012
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yosuke Ota, Yoshiro Hirose, Atsushi Sano, Osamu Kasahara, Kazuyuki Okuda, Kiyohiko Maeda
  • Publication number: 20120064733
    Abstract: Provided is a method of manufacturing a semiconductor device, including: forming a silicon oxide film on a surface of a substrate holder by repeatedly performing forming a silicon-containing layer on the surface of the substrate holder and oxidizing the silicon-containing layer; forming a thin film on a substrate by using a process gas; removing deposits attached onto the substrate holder by using a fluorine-containing gas; and reforming a silicon oxide film on the surface of the substrate holder after removal of the deposits by repeatedly performing forming a silicon-containing layer on the surface of the substrate holder and oxidizing the silicon-containing layer by using an oxygen-containing gas and a hydrogen-containing gas.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 15, 2012
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Ryota SASAJIMA, Yoshiro HIROSE, Naonori AKAE, Osamu KASAHARA
  • Publication number: 20110212625
    Abstract: A substrate processing apparatus which is capable of improving a manufacture yield while processing a substrate with high precision, and a method of manufacturing a semiconductor device. The substrate processing apparatus includes a substrate support part provided within a process chamber and configured to support a substrate; a substrate support moving mechanism configured to move the substrate support part; a gas feeding part configured to feed a gas into the process chamber; an exhaust part configured to exhaust the gas within the process chamber; and a plasma generating part disposed to face the substrate support part.
    Type: Application
    Filed: February 25, 2011
    Publication date: September 1, 2011
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kazuyuki TOYODA, Osamu KASAHARA, Yoshiro HIROSE, Hiroyuki TAKADERA, Daigi KAMIMURA
  • Publication number: 20110207302
    Abstract: Embodiments described herein relate to improving the quality of a substrate and the performance of a semiconductor device, which is caused by contaminates or particles being engrained into a substrate with a silicon film formed thereon, and forming a silicon film with a small surface roughness. Provided is a semiconductor device manufacturing method that includes forming a silicon film on a substrate, supplying an oxidation seed onto the substrate, performing heat treatment on the silicon film, modifying the surface layer of the silicon film into an oxidized silicon film, and removing the oxidized silicon film.
    Type: Application
    Filed: February 23, 2011
    Publication date: August 25, 2011
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Jie WANG, Osamu KASAHARA, Kazuhiro YUASA, Keigo NISHIDA
  • Publication number: 20090117752
    Abstract: A high quality interface is formed at a low oxygen-carbon density between a substrate and a thin film while preventing heat damage on the substrate and increase of thermal budget. This method includes a step of loading a wafer into a reaction furnace, a step of pretreating the wafer in the reaction furnace, a step of performing a main processing of the pretreated wafer in the reaction furnace, and a step of unloading the wafer from the reaction furnace after the main processing. Hydrogen gas is continuously supplied to the reaction furnace in the period from the end of the pretreating step to the start of the main processing and at least during vacuum-exhausting an interior of the reaction furnace.
    Type: Application
    Filed: November 2, 2005
    Publication date: May 7, 2009
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takashi Ozaki, Osamu Kasahara, Takaaki Noda, Kiyohiko Maeda, Atsushi Moriya, Minoru Sakamoto
  • Patent number: 7494941
    Abstract: At a time of a substrate loading step or/and at a time of a substrate unloading step, particles are effectively eliminated from a reaction chamber. Provided are a step of loading at least one wafer 200 into a reaction chamber 201, a step of introducing reaction gas into the reaction chamber 201, and exhausting an inside of the reaction chamber 201, thereby processing the wafer 200, and a step of unloading the processed wafer 200 from the reaction chamber 201. In the step of loading the wafer 200 or/and in the step of unloading the wafer 200, the inside of the reaction chamber 201 is exhausted at a larger exhaust flow rate than an exhaust flow rate in the step of processing the wafer 200.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: February 24, 2009
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Osamu Kasahara, Kiyohiko Maeda, Akihiko Yoneda
  • Publication number: 20070032045
    Abstract: At a time of a substrate loading step or/and at a time of a substrate unloading step, particles are effectively eliminated from a reaction chamber. Provided are a step of loading at least one wafer 200 into a reaction chamber 201, a step of introducing reaction gas into the reaction chamber 201, and exhausting an inside of the reaction chamber 201, thereby processing the wafer 200, and a step of unloading the processed wafer 200 from the reaction chamber 201. In the step of loading the wafer 200 or/and in the step of unloading the wafer 200, the inside of the reaction chamber 201 is exhausted at a larger exhaust flow rate than an exhaust flow rate in the step of processing the wafer 200.
    Type: Application
    Filed: November 19, 2004
    Publication date: February 8, 2007
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Osamu Kasahara, Kiyohiko Maeda, Akihiko Yoneda
  • Patent number: 7033937
    Abstract: An apparatus for use in manufacturing a semiconductor device allows one or more substrates treated substantially free of the metal particles released from the chamber wall and the high energy particles emitted from the plasma and also allows them to uniformly heated to a relatively high temperature. The apparatus comprises a reaction chamber wherein one or more substrates to be treated are disposed, a plasma source arranged outside of and in proximity to the reaction chamber, an active species supply port for providing active species generated by the plasma source to the reaction chamber and arranged at a side of the reaction chamber and an exhaust port provided at the opposite side to the active species supply port. The active species flows parallel to the surfaces of the substrates.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: April 25, 2006
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Kazuyuki Toyoda, Osamu Kasahara, Tsutomu Tanaka, Mamoru Sueyoshi, Nobuhito Shima, Masanori Sakai
  • Patent number: 6894334
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: May 17, 2005
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Publication number: 20030189255
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Application
    Filed: March 3, 2003
    Publication date: October 9, 2003
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Publication number: 20030124876
    Abstract: An apparatus for use in manufacturing a semiconductor device allows one or more substrates treated substantially free of the metal particles released from the chamber wall and the high energy particles emitted from the plasma and also allows them to uniformly heated to a relatively high temperature. The apparatus comprises a reaction chamber wherein one or more substrates to be treated are disposed, a plasma source arranged outside of and in proximity to the reaction chamber, an active species supply port for providing active species generated by the plasma source to the reaction chamber and arranged at a side of the reaction chamber and an exhaust port provided at the opposite side to the active species supply port. The active species flows parallel to the surfaces of the substrates.
    Type: Application
    Filed: January 14, 2003
    Publication date: July 3, 2003
    Inventors: Kazuyuki Toyoda, Osamu Kasahara, Tsutomu Tanaka, Mamoru Sueyoshi, Nobuhito Shima, Masanori Sakai