Abstract: A device includes a substrate having a base member and an insulation film formed on a surface of the base member, a first semiconductor chip mounted over a surface of the substrate on which the insulation film are formed, a second semiconductor chip stacked over the first semiconductor chip so that an overhang portion is formed, and a sealing member formed on the substrate so that the first semiconductor chip and the second semiconductor chip are covered with the sealing member. The insulation film has a first opening portion in a first area of the substrate that overlaps the overhang portion. The base member has an air passage communicating with the first opening portion.

Abstract: A device includes a substrate having a base member and an insulation film formed on a surface of the base member, a first semiconductor chip mounted over a surface of the substrate on which the insulation film are formed, a second semiconductor chip stacked over the first semiconductor chip so that an overhang portion is formed, and a sealing member formed on the substrate so that the first semiconductor chip and the second semiconductor chip are covered with the sealing member. The insulation film has a first opening portion in a first area of the substrate that overlaps the overhang portion. The base member has an air passage communicating with the first opening portion.

Abstract: A wiring board of this invention includes a product formation area in which are arranged a plurality of product formation sections on which a semiconductor chip is mounted; a molding area that is provided on an outer circumferential side of the product formation area, and with which a seal portion that covers the semiconductor chips mounted on the product formation sections makes contact; a clamp area that is provided on an outer circumferential side of the molding area, and that is held by a molding die that forms the seal portion; wiring that is provided in the product formation area, and that is electrically connected to the semiconductor chips; a first solid pattern that is provided in the molding area, and in which a plurality of dots are arranged; and a second solid pattern that is provided in the clamp area, and in which a plurality of dots that are larger than the dots of the first solid pattern are arranged.

Abstract: A wiring board of this invention includes a product formation area in which are arranged a plurality of product formation sections on which a semiconductor chip is mounted; a molding area that is provided on an outer circumferential side of the product formation area, and with which a seal portion that covers the semiconductor chips mounted on the product formation sections makes contact; a clamp area that is provided on an outer circumferential side of the molding area, and that is held by a molding die that forms the seal portion; wiring that is provided in the product formation area, and that is electrically connected to the semiconductor chips; a first solid pattern that is provided in the molding area, and in which a plurality of dots are arranged; and a second solid pattern that is provided in the clamp area, and in which a plurality of dots that are larger than the dots of the first solid pattern are arranged.

Abstract: The present invention includes a first recognition mark which is arranged in a frame part of a perimeter of an implementation region having a plurality of semiconductor chips implemented therein so that the position of the semiconductor substrate can be macroscopically detected by using a recognition camera, and a second recognition mark which is formed into a smaller shape than the first recognition mark so that the position of the dividing line can be microscopically detected by using a recognition camera. The second recognition mark is arranged so that its center line is positioned on a line that extends from a dicing line, and has a pattern shape which is formed so as to be linearly symmetric with respect to the center line. This pattern shape is formed so that the ratio of a length occupying a direction parallel to the dicing line is larger than that occupying a direction perpendicular to the dicing line, and includes a flow region for promoting the flow of an etchant for forming the pattern shape.

Abstract: The present invention includes a first recognition mark which is arranged in a frame part of a perimeter of an implementation region having a plurality of semiconductor chips implemented therein so that the position of the semiconductor substrate can be macroscopically detected by using a recognition camera, and a second recognition mark which is formed into a smaller shape than the first recognition mark so that the position of the dividing line can be microscopically detected by using a recognition camera. The second recognition mark is arranged so that its center line is positioned on a line that extends from a dicing line, and has a pattern shape which is formed so as to be linearly symmetric with respect to the center line. This pattern shape is formed so that the ratio of a length occupying a direction parallel to the dicing line is larger than that occupying a direction perpendicular to the dicing line, and includes a flow region for promoting the flow of an etchant for forming the pattern shape.