Patents by Inventor Osamu Koike

Osamu Koike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11938731
    Abstract: A substrate, a diaphragm, and a piezoelectric actuator are laminated in this order in a first direction, the diaphragm includes a first layer containing silicon as a constituent element, a second layer disposed between the first layer and the piezoelectric actuator, and containing any one or both of at least one metal element selected from the group made of chromium, titanium, aluminum, tantalum, hafnium, and iridium, and silicon nitride, as a constituent element, and a third layer disposed between the second layer and the piezoelectric actuator and containing zirconium as a constituent element, and a fourth layer containing any one or both of at least one metal element selected from the group made of chromium, titanium, aluminum, tantalum, hafnium, and iridium, and silicon nitride, as a constituent element is provided on the third layer on a piezoelectric actuator side.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Seiko Epson Corporation
    Inventors: Harunobu Koike, Masao Nakayama, Toshihiro Shimizu, Yasushi Yamazaki, Osamu Tonomura, Tatsuo Sawasaki, Chihiro Nishi
  • Publication number: 20240071971
    Abstract: A semiconductor device includes a semiconductor substrate having a surface with a metal wiring on the surface, an insulating film that covers the surface of the semiconductor substrate, and a plurality of electrodes disposed on the insulating film and having mutually same planar shapes. The insulating film has a plurality of opening portions formed to face respective bottom surfaces of the plurality of electrodes and expose the metal wiring. The plurality of opening portions includes a first opening portion having a first planar configuration and a second opening portion having a second planar configuration different from the first planar configuration.
    Type: Application
    Filed: August 25, 2023
    Publication date: February 29, 2024
    Applicant: LAPIS Technology Co., Ltd.
    Inventor: Osamu KOIKE
  • Publication number: 20230386922
    Abstract: A semiconductor device includes a semiconductor substrate, active elements, first insulating film, an electrode pad, and a Through Silicon VIA electrode. The semiconductor substrate has an obverse surface and a reverse surface. The active elements define an element-absence area free of any of the active elements. The element-absence area includes a second insulating film, a ring-shaped dummy portion, and island-shaped dummy portions. The ring-shaped dummy portion and the island-shaped dummy portions are made of the same material as the semiconductor substrate. The ring-shaped dummy portion and the island-shaped dummy portions have top surfaces coplanar with a top surface of the second insulating film. The Through Silicon VIA electrode penetrates between an inner edge and an outer edge of the ring-shaped dummy portion from the reverse surface to the obverse surface. Some island-shaped dummy portions are disposed inside of the inner edge of the ring-shaped dummy portion.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Osamu KOIKE, Yutaka KADOGAWA
  • Patent number: 11798847
    Abstract: There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: October 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Osamu Koike, Yutaka Kadogawa
  • Publication number: 20210098297
    Abstract: There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.
    Type: Application
    Filed: December 10, 2020
    Publication date: April 1, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Osamu KOIKE, Yutaka KADOGAWA
  • Patent number: 10957638
    Abstract: A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: March 23, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Osamu Koike
  • Patent number: 10892189
    Abstract: There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: January 12, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Osamu Koike, Yutaka Kadogawa
  • Publication number: 20190363041
    Abstract: A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.
    Type: Application
    Filed: August 8, 2019
    Publication date: November 28, 2019
    Inventor: OSAMU KOIKE
  • Publication number: 20190326173
    Abstract: There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Osamu KOIKE, Yutaka KADOGAWA
  • Patent number: 10424537
    Abstract: A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: September 24, 2019
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Osamu Koike
  • Publication number: 20180151434
    Abstract: There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.
    Type: Application
    Filed: January 24, 2018
    Publication date: May 31, 2018
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Osamu KOIKE, Yutaka KADOGAWA
  • Patent number: 9892968
    Abstract: There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: February 13, 2018
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Osamu Koike, Yutaka Kadogawa
  • Publication number: 20170287824
    Abstract: A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 5, 2017
    Inventor: OSAMU KOIKE
  • Patent number: 9721879
    Abstract: A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: August 1, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Osamu Koike
  • Patent number: 9293402
    Abstract: A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: March 22, 2016
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Osamu Koike
  • Publication number: 20160013145
    Abstract: A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.
    Type: Application
    Filed: September 22, 2015
    Publication date: January 14, 2016
    Inventor: OSAMU KOIKE
  • Publication number: 20130270697
    Abstract: A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to any of the substrate and the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part to the top part to connect the bottom part and the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, the ring-like projection part being formed in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.
    Type: Application
    Filed: April 11, 2013
    Publication date: October 17, 2013
    Applicant: LAPIS SEMICONDUTOR CO., LTD.
    Inventor: OSAMU KOIKE
  • Patent number: 8183147
    Abstract: A method of fabricating a semiconductor device includes: forming a semiconductor chip portion having an electrode on a main surface of a wafer; forming a first resist pattern having a first opening on the electrode; filling the first opening with a first electrically conductive material, thereby forming an electrically conductive post; removing the first resist pattern after said forming of the electrically conductive post; forming an interlayer dielectric film having a second opening positioned on the electrically conductive post; and forming an electrically conductive redistribution layer extending from an upper surface of the electrically conductive post over an upper surface of the interlayer dielectric film.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: May 22, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Osamu Koike
  • Patent number: 8008195
    Abstract: An insulator layer is formed on a part of semiconductor substrate to form an isolation layer that insulates and separates active elements from each other in the first region, and to form a dummy portion which is composed of a base material of the semiconductor substrate exposed in the insulator layer in a second region. Active elements are formed in the first region. A silicide layer is formed on the first and second regions excluding at least a portion in which the TSV electrode should be formed. At least one TSV hole extending from a reverse surface side of the semiconductor substrate to an electrode pad via the second region is formed. A conductive film is formed on the inner wall of the TSV hole to form a TSV electrode electrically connected to the electrode pad.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: August 30, 2011
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Osamu Koike, Yutaka Kadogawa
  • Publication number: 20110198748
    Abstract: A method of fabricating a semiconductor device includes: forming a semiconductor chip portion having an electrode on a main surface of a wafer; forming a first resist pattern having a first opening on the electrode; filling the first opening with a first electrically conductive material, thereby forming an electrically conductive post; removing the first resist pattern after said forming of the electrically conductive post; forming an interlayer dielectric film having a second opening positioned on the electrically conductive post; and forming an electrically conductive redistribution layer extending from an upper surface of the electrically conductive post over an upper surface of the interlayer dielectric film.
    Type: Application
    Filed: February 14, 2011
    Publication date: August 18, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Osamu Koike