Abstract: A semiconductor device that has a feature in the spatial relationship between the wiring in a multi-level wiring and the intermediate insulating films. In the lower part of the second and/or subsequent levels of wiring there exist intermediate insulating films that have a pattern which is the same as the pattern of the wiring. Because of this arrangement, the intermediate insulating film does not exist between the wiring on the same level. The first structure of the multi-level wiring has the intermediate insulating films formed in wall-like shape, with the lower end of the intermediate insulating films reaching an underlying insulating layer formed on the surface of the semiconductor substrate. The second structure of the multi-level wiring is a quasi air gap metallization structure.

Abstract: An interlayer connection structure for an integrated circuit includes a substrate, a first level horizontal conductor formed on the substrate, an interlayer insulator formed to cover the first level conductor, a second level horizontal conductor formed on the interlayer insulator, and a vertical conductive pillar extending through the interlayer insulator for interconnecting the first level horizontal conductor and the second level horizontal conductor. The vertical conductive pillar has a side surface coplanar with a longitudinal side surface of the first level horizontal conductor at a position where the vertical conductive pillar is in electric contact with the first level horizontal conductor.

Abstract: Disclosed herein is a semiconductor device including a thin-film-transistor which comprises a silicon film formed on an insulating layer and including a substrate area, a gate provided to form a channel in the substrate area, a source consisting of a first metal silicide film forming a Schottky barrier with the substrate area, and a drain including a second metal silicide film. The second metal silicide film forms a Schottky barrier with the substrate area or is in ohmic contact with an impurity region selectively formed in the silicon film with a PN junction with the substrate area.