Abstract: A memory device provided with a redundant scheme in which a leakage current and unnecessary power consumption due to defective memory cells are suppressed is disclosed. The memory device has an array of memory cells which are divided into a plurality of sections, and a branch power supply line is provided between each section and adapted to be connected to a common power supply line, the branch power supply line for a defective section including defective memory cell being cut to electrically isolate the defective section from the common power supply line.

Abstract: An insulated gate type field effect transistor forming one cell of a high density integrated circuit semiconductor memory device and a method for producing the same are disclosed. A channel stopper region of the same conductivity type as the substrate but having a higher impurity concentration is disposed contiguous to the width edge of the channel region, and a thick field oxide film is provided outside of the channel stopper region. The channel stopper region is self-aligned with the width edges of the gate electrode, and an insulator film having a thinner film thickness than that of the thick field oxide film is formed on the channel stopper region. In one embodiment, a second channel stopper region similar to the first is provided at the surface of the substrate under the field oxide film. A capacitor region is associated with the field effect transistor, and together they form a memory cell which is substantially surrounded by an isolating region including the thick field oxide film.

Abstract: A memory circuit suitable for large scale integration is disclosed. The memory circuit comprises a plurality of memory cells each including a gate transistor having a gate coupled to one of word lines and a drain coupled to one of digit lines and capacitor means coupled between a source of the gate transistor and a potential source, wherein the threshold voltage of the gate transistors is made smaller than that of logic transistors employed in peripheral circuits.

Abstract: An insulated gate type field effect transistor forming one cell of a high density integrated circuit semiconductor memory device and a method for producing the same are disclosed. A channel stopper region of the same conductivity type as the substrate but having a higher impurity concentration is disposed contiguous to the width edge of the channel region, and a thick field oxide film is provided outside of the channel stopper region. The channel stopper region is self-aligned with the width edges of the gate electrode, and an insulator film having a thinner film thickness than that of the thick field oxide film is formed on the channel stopper region. In one embodiment, a second channel stopper region similar to the first is provided at the surface of the substrate under the field oxide film. A capacitor region is associated with the field effect transistor, and together they form a memory cell which is substantially surrounded by an isolating region including the thick field oxide film.