Abstract: A protection device includes: a serial element unit that includes a first switching element and a resistive element, one end being connected to a control terminal of a protection-target switching element, the other end being connected to a first voltage line, the protection-target switching element including a first terminal connected to the first voltage line, a second terminal connected to a second voltage line and an inductor unit, and the control terminal, the protection-target switching element switching a conduction state at the normal time to a non-conduction state between the first terminal and the second terminal when an off-voltage is applied to the control terminal; a capacitance provided at the protection-target switching element and has a predetermined capacitance value; and a controller that performs control such that the first switching element is in a conduction state if the protection-target switching element is put into a non-conduction state.

Abstract: A signal amplifier includes an inverting amplification circuit, a first switching element, a second switching element, and a control section. The inverting amplification circuit includes a first voltage terminal, a second voltage terminal, an inverting input terminal, an output terminal, a first protected switching element, and a second protected switching element. The control section controls such that when an overcurrent has flowed in the first voltage line, the first and second protected switching elements are switched to a non-conducting state after switching the first switching element in a conducting state and switching the second switching element in a non-conducting state, and when an overcurrent has flowed in the second voltage line, the first the second protected switching elements are switched to a non-conducting state after switching the first switching element in a non-conducting state and switching the second switching element in a conducting state.

Abstract: A protection device includes: a serial element unit that includes a first switching element and a resistive element, one end being connected to a control terminal of a protection-target switching element, the other end being connected to a first voltage line, the protection-target switching element including a first terminal connected to the first voltage line, a second terminal connected to a second voltage line and an inductor unit, and the control terminal, the protection-target switching element switching a conduction state at the normal time to a non-conduction state between the first terminal and the second terminal when an off-voltage is applied to the control terminal; a capacitance provided at the protection-target switching element and has a predetermined capacitance value; and a controller that performs control such that the first switching element is in a conduction state if the protection-target switching element is put into a non-conduction state.

Abstract: A bias generation circuit is between a power voltage node and ground voltage node at a far end from power voltage and ground voltage terminals. Reference voltage nodes are connected to an amplifier circuit block from the far end. The amplifier block is closer to the power supply source, and the bias generation circuit is distant therefrom. Even if the power supply voltage drops due to current constantly flowing in the amplification block and bias generation circuit, the bias generation circuit generates reference voltages at the reference voltage nodes based on the voltage-dropped power supply. Therefore, the voltage in the constant current source MOS transistor of the amplifier block becomes lowest at the amplifier circuit closest to the bias generation circuit. The response speeds of other amplifier circuits do not drop if the circuit is designed based on the amplifier closest to the bias generation circuit.

Abstract: A column decoder in a semiconductor memory device in which address setting cannot be performed but only a serial access can be performed. The column decoder is constructed by: a redundant fuse for generating a redundant fuse signal; a column decoding circuit for decoding a column address; a column decoding switching circuit for switching an output destination of a decoding result of the column decoding circuit by the redundant fuse signal; and a column driver for driving an output signal of the column decoding switching circuit and generating it to normal column lines and a redundant column line. The column decoding circuit continuously makes the redundant column line operative after the operation of the normal column lines.

Abstract: A semiconductor integrated circuit has a bias generation circuit. The bias generation circuit is placed between a power supply voltage node and ground voltage node which are at a far end from a power supply voltage supply terminal and ground voltage supply terminal. Reference voltage nodes are connected to an amplifier circuit block from the far end. In an actual chip layout, the amplifier circuit block is placed closer to the power supply source, and the bias generation circuit is placed distant therefrom. Even if the power supply voltage drops due to current constantly flowing in the amplification circuit block and bias generation circuit, the bias generation circuit generates reference voltages at the reference voltage nodes based on the voltage-dropped power supply. Therefore, the voltage in the constant current source MOS transistor of the amplifier circuit block becomes lowest at the amplifier circuit which is closest to the bias generation circuit.

Abstract: [Object] This invention provides a dispersion containing an insect pest repellent active substance, and an adhesive or bond, ink, resin pellets, a resin product, and a sheet or a film which can exhibit a long term repellent active effect by the particles carrying the dispersion.

Abstract: A field memory includes a memory cell array, a first decoder, a second decoder, a sense amplifier circuit, a transfer gate circuit, a write register and a read register. The memory cell array has a field memory for storing data and a line memory for temporarily storing data. The first decoder is coupled to the field memory for selecting a memory cell in the field memory. The second decoder is coupled to the line memory for selecting a memory cell in the line memory. The sense amplifier circuit is coupled to the, memory cell array. The transfer gate circuit is coupled to the sense amplifier circuit. The write register is coupled to the transfer gate circuit for temporarily storing data to be written in the memory cell array. The first read register is coupled to the transfer gate circuit for temporarily storing data read from the memory cell array.

Abstract: A column decoder in a semiconductor memory device in which address setting cannot be performed but only a serial access can be performed. The column decoder is constructed by: a redundant fuse for generating a redundant fuse signal; a column decoding circuit for decoding a column address; a column decoding switching circuit for switching an output destination of a decoding result of the column decoding circuit by the redundant fuse signal; and a column driver for driving an output signal of the column decoding switching circuit and generating it to normal column lines and a redundant column line. The column decoding circuit continuously makes the redundant column line operative after the operation of the normal column lines.

Abstract: A field memory includes a memory cell array, a first decoder, a second decoder, a sense amplifier circuit, a transfer gate circuit, a write register and a read register. The memory cell array has a field memory for storing data and a line memory for temporally storing data. The first decoder is coupled to the field memory for selecting memory cell in the field memory. The second decoder is coupled to the line memory for selecting memory cell in the line memory. The sense amplifier circuit is coupled to the memory cell array. The transfer gate circuit is coupled to the sense amplifier circuit. The write register is coupled to the transfer gate circuit for temporally storing data to be written in the memory cell array. The first read register is coupled to the transfer gate circuit for temporally storing data read from the memory cell array.

Abstract: A semiconductor memory device includes a memory circuit which stores data, a control circuit which outputs a data and a control signal to control the memory circuit and which receives a data stored in the memory circuit, and a selector circuit which selectively transfers either one of the data output from the control circuit or external data output from an external device to the memory circuit in response to a selection signal. The memory circuit, the control circuit, and the selector circuit in the semiconductor memory device are formed on a single chip.

Abstract: A field memory includes a DRAM core, a processor that generates and supplies a RAS control signal to the DRAM core, and a RAS cycle monitor circuit. The RAS cycle monitor circuit includes a counter circuit that counts the number of cycles of a RAS control signal supplied to a DRAM core in a predetermined period of time, and a monitor circuit that detects whether the number of cycles of the RAS control signal is within a normal operating range. The monitor circuit supplies a monitor output signal to indicate whether the RAS control signal is being generated on a proper cycle.

Abstract: Column signals CL1˜CLm generated in a Y decoder circuit 31 are selectively output to a sub-register block 10S or a resister block 10R, based on enabling signals SEN and REN. Then, write-in data is stored in the sub-register block 10S or the resister block 10R or read-out data is obtained from the sub-register block 10S or the resister block 10R. By structuring in this way, it is possible to reduce the scale of a circuit of a semiconductor device and lessen the chip size.

Abstract: A first data store circuit is coupled to first and second voltage nodes of first and second voltage levels, respectively, and a control circuit outputs a transfer signal and a switching signal. A data transfer circuit is coupled between the first data store circuit and a second data store circuit and selectively transfers the data in the first data store circuit to the second data store circuit in response to the transfer signal. A first conductive line supplies the first voltage level to the second data store circuit and a second conductive line supplies the second voltage level to the second data store circuit. A first switch circuit is coupled between the second voltage node and the second conductive line and selectively connects the second voltage node to the second conductive line in response to the switching signal. Also a resistive element is coupled between the second conductive line and the first voltage node.