Patents by Inventor Osamu Miyagawa
Osamu Miyagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200091173Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate and a stack body including first films and second films alternately stacked in a first direction perpendicular to the semiconductor substrate, and including a stepped end portion. Each of the first films has a thick film portion located on the end portion, and an eave portion hanging over from a upper part of the thick film portion to the side in a second direction parallel to the semiconductor substrate.Type: ApplicationFiled: February 21, 2019Publication date: March 19, 2020Applicant: Toshiba Memory CorporationInventors: Osamu MIYAGAWA, Takahiro TOMIMATSU
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Patent number: 9761415Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a housing configured to house a substrate, and a first temperature regulator configured to regulate a temperature of a fluid. The apparatus further includes first and second flow channels configured to divide the fluid supplied from the first temperature regulator, and a second temperature regulator configured to regulate a temperature of the fluid in the second channel. The apparatus further includes a fluid supply channel configured to join the fluid in the first flow channel and the fluid in the second flow channel and to supply the joined fluids to the housing, and a flow rate regulator configured to regulate a flow rate of the fluid in the first flow channel and a flow rate of the fluid in the second flow channel.Type: GrantFiled: September 3, 2015Date of Patent: September 12, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventor: Osamu Miyagawa
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Publication number: 20160284521Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a housing configured to house a substrate, and a first temperature regulator configured to regulate a temperature of a fluid. The apparatus further includes first and second flow channels configured to divide the fluid supplied from the first temperature regulator, and a second temperature regulator configured to regulate a temperature of the fluid in the second channel. The apparatus further includes a fluid supply channel configured to join the fluid in the first flow channel and the fluid in the second flow channel and to supply the joined fluids to the housing, and a flow rate regulator configured to regulate a flow rate of the fluid in the first flow channel and a flow rate of the fluid in the second flow channel.Type: ApplicationFiled: September 3, 2015Publication date: September 29, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Osamu MIYAGAWA
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Patent number: 8908117Abstract: A thin film transistor array substrate of the present invention having an array area, and a frame area, the thin film transistor array substrate includes: a thin film transistor; an upper metal pattern formed by the same material as source and drain electrodes at the same layer; a transparent conductive film pattern; and an upper layer insulation film, wherein the transparent conductive film pattern has: a first-type transparent conductive film pattern provided to located within one of a pattern of the electrode pattern and a pattern of the metal pattern, as viewed from the top side, and to not cover pattern end faces of the electrode pattern or the metal pattern; and a second-type transparent conductive film pattern provided to stick out from an inside of at least a portion of one of the patterns, as viewed from the top side and to cover the pattern end faces.Type: GrantFiled: October 26, 2011Date of Patent: December 9, 2014Assignee: Mitsubishi Electric CorporationInventors: Masami Hayashi, Osamu Miyagawa, Toru Takeguchi, Shinichi Yano, Yasuyoshi Itoh, Shingo Nagano
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Patent number: 8815726Abstract: A method of manufacturing a semiconductor device including forming a mask layer on a polycrystalline silicon film formed on a semiconductor substrate via an insulating film; forming a dense pattern and a sparse pattern on the mask layer to form a mask; etching the polycrystalline silicon film with the mask by controlling a temperature of the semiconductor substrate placed in an etching chamber at 50 degrees Celsius or higher, supplying an etching gas composed of a hydrogen bromide containing gas and a fluoromethane based gas into the chamber, and generating plasma in the chamber.Type: GrantFiled: June 20, 2011Date of Patent: August 26, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Osamu Miyagawa
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Publication number: 20120113376Abstract: A thin film transistor array substrate of the present invention having an array area, and a frame area, the thin film transistor array substrate includes: a thin film transistor; an upper metal pattern formed by the same material as source and drain electrodes at the same layer; a transparent conductive film pattern; and an upper layer insulation film, wherein the transparent conductive film pattern has: a first-type transparent conductive film pattern provided to located within one of a pattern of the electrode pattern and a pattern of the metal pattern, as viewed from the top side, and to not cover pattern end faces of the electrode pattern or the metal pattern; and a second-type transparent conductive film pattern provided to stick out from an inside of at least a portion of one of the patterns, as viewed from the top side and to cover the pattern end faces.Type: ApplicationFiled: October 26, 2011Publication date: May 10, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Masami HAYASHI, Osamu Miyagawa, Toru Takeguchi, Shinichi Yano, Yasuyoshi Itoh, Shingo Nagano
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Publication number: 20110244672Abstract: A method of manufacturing a semiconductor device including forming a mask layer on a polycrystalline silicon film formed on a semiconductor substrate via an insulating film; forming a dense pattern and a sparse pattern on the mask layer to form a mask; etching the polycrystalline silicon film with the mask by controlling a temperature of the semiconductor substrate placed in an etching chamber at 50 degrees Celsius or higher, supplying an etching gas composed of a hydrogen bromide containing gas and a fluoromethane based gas into the chamber, and generating plasma in the chamber.Type: ApplicationFiled: June 20, 2011Publication date: October 6, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Osamu MIYAGAWA
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Patent number: 7989331Abstract: A method of manufacturing a semiconductor device including forming a mask layer on a polycrystalline silicon film formed on a semiconductor substrate via an insulating film; forming a dense pattern and a sparse pattern on the mask layer to form a mask; etching the polycrystalline silicon film with the mask by controlling a temperature of the semiconductor substrate placed in an etching chamber at 50 degrees Celsius or higher, supplying an etching gas composed of a hydrogen bromide containing gas and a fluoromethane based gas into the chamber, and generating plasma in the chamber.Type: GrantFiled: October 9, 2007Date of Patent: August 2, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Osamu Miyagawa
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Publication number: 20080085593Abstract: A method of manufacturing a semiconductor device including forming a mask layer on a polycrystalline silicon film formed on a semiconductor substrate via an insulating film; forming a dense pattern and a sparse pattern on the mask layer to form a mask; etching the polycrystalline silicon film with the mask by controlling a temperature of the semiconductor substrate placed in an etching chamber at 50 degrees Celsius or higher, supplying an etching gas composed of a hydrogen bromide containing gas and a fluoromethane based gas into the chamber, and generating plasma in the chamber.Type: ApplicationFiled: October 9, 2007Publication date: April 10, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Osamu MIYAGAWA
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Patent number: 7312158Abstract: A method of forming a pattern, including forming first and second films, and a resist film on the second film, patterning the resist film to form a first pattern, etching the first pattern to narrow a width of the lines of the first pattern, etching the second film by using the first pattern as a mask to form a second pattern having a configuration of the first pattern transferred thereto, forming a third film above the substrate to cover the second pattern, filling a recessed portion of the third film corresponding to a gap between the lines of the second pattern with a fourth film, and removing a portion of the third film which is located on opposite sides of the fourth film, and a portion of the first film which is located below the third film to form a third pattern.Type: GrantFiled: March 13, 2006Date of Patent: December 25, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Miyagawa, Hideki Oguma
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Publication number: 20060216938Abstract: A method of forming a pattern, including forming first and second films, and a resist film on the second film, patterning the resist film to form a first pattern, etching the first pattern to narrow a width of the lines of the first pattern, etching the second film by using the first pattern as a mask to form a second pattern having a configuration of the first pattern transferred thereto, forming a third film above the substrate to cover the second pattern, filling a recessed portion of the third film corresponding to a gap between the lines of the second pattern with a fourth film, and removing a portion of the third film which is located on opposite sides of the fourth film, and a portion of the first film which is located below the third film to form a third pattern.Type: ApplicationFiled: March 13, 2006Publication date: September 28, 2006Inventors: Osamu Miyagawa, Hideki Oguma
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Publication number: 20050215062Abstract: A method of manufacturing a semiconductor device involves etching a film of a metal oxide formed above a semiconductor substrate, by using an etching gas. The etching gas includes a reducing gas which is capable of reducing the metal oxide and is non-reactive with the metal, and a reactive gas which is capable of etching the metal.Type: ApplicationFiled: March 15, 2005Publication date: September 29, 2005Inventors: Osamu Miyagawa, Masaki Narita, Tokuhisa Ohiwa