Patents by Inventor Osamu Miyagawa

Osamu Miyagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200091173
    Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate and a stack body including first films and second films alternately stacked in a first direction perpendicular to the semiconductor substrate, and including a stepped end portion. Each of the first films has a thick film portion located on the end portion, and an eave portion hanging over from a upper part of the thick film portion to the side in a second direction parallel to the semiconductor substrate.
    Type: Application
    Filed: February 21, 2019
    Publication date: March 19, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Osamu MIYAGAWA, Takahiro TOMIMATSU
  • Patent number: 9761415
    Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a housing configured to house a substrate, and a first temperature regulator configured to regulate a temperature of a fluid. The apparatus further includes first and second flow channels configured to divide the fluid supplied from the first temperature regulator, and a second temperature regulator configured to regulate a temperature of the fluid in the second channel. The apparatus further includes a fluid supply channel configured to join the fluid in the first flow channel and the fluid in the second flow channel and to supply the joined fluids to the housing, and a flow rate regulator configured to regulate a flow rate of the fluid in the first flow channel and a flow rate of the fluid in the second flow channel.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: September 12, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Osamu Miyagawa
  • Publication number: 20160284521
    Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a housing configured to house a substrate, and a first temperature regulator configured to regulate a temperature of a fluid. The apparatus further includes first and second flow channels configured to divide the fluid supplied from the first temperature regulator, and a second temperature regulator configured to regulate a temperature of the fluid in the second channel. The apparatus further includes a fluid supply channel configured to join the fluid in the first flow channel and the fluid in the second flow channel and to supply the joined fluids to the housing, and a flow rate regulator configured to regulate a flow rate of the fluid in the first flow channel and a flow rate of the fluid in the second flow channel.
    Type: Application
    Filed: September 3, 2015
    Publication date: September 29, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Osamu MIYAGAWA
  • Patent number: 8908117
    Abstract: A thin film transistor array substrate of the present invention having an array area, and a frame area, the thin film transistor array substrate includes: a thin film transistor; an upper metal pattern formed by the same material as source and drain electrodes at the same layer; a transparent conductive film pattern; and an upper layer insulation film, wherein the transparent conductive film pattern has: a first-type transparent conductive film pattern provided to located within one of a pattern of the electrode pattern and a pattern of the metal pattern, as viewed from the top side, and to not cover pattern end faces of the electrode pattern or the metal pattern; and a second-type transparent conductive film pattern provided to stick out from an inside of at least a portion of one of the patterns, as viewed from the top side and to cover the pattern end faces.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: December 9, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masami Hayashi, Osamu Miyagawa, Toru Takeguchi, Shinichi Yano, Yasuyoshi Itoh, Shingo Nagano
  • Patent number: 8815726
    Abstract: A method of manufacturing a semiconductor device including forming a mask layer on a polycrystalline silicon film formed on a semiconductor substrate via an insulating film; forming a dense pattern and a sparse pattern on the mask layer to form a mask; etching the polycrystalline silicon film with the mask by controlling a temperature of the semiconductor substrate placed in an etching chamber at 50 degrees Celsius or higher, supplying an etching gas composed of a hydrogen bromide containing gas and a fluoromethane based gas into the chamber, and generating plasma in the chamber.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Osamu Miyagawa
  • Publication number: 20120113376
    Abstract: A thin film transistor array substrate of the present invention having an array area, and a frame area, the thin film transistor array substrate includes: a thin film transistor; an upper metal pattern formed by the same material as source and drain electrodes at the same layer; a transparent conductive film pattern; and an upper layer insulation film, wherein the transparent conductive film pattern has: a first-type transparent conductive film pattern provided to located within one of a pattern of the electrode pattern and a pattern of the metal pattern, as viewed from the top side, and to not cover pattern end faces of the electrode pattern or the metal pattern; and a second-type transparent conductive film pattern provided to stick out from an inside of at least a portion of one of the patterns, as viewed from the top side and to cover the pattern end faces.
    Type: Application
    Filed: October 26, 2011
    Publication date: May 10, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masami HAYASHI, Osamu Miyagawa, Toru Takeguchi, Shinichi Yano, Yasuyoshi Itoh, Shingo Nagano
  • Publication number: 20110244672
    Abstract: A method of manufacturing a semiconductor device including forming a mask layer on a polycrystalline silicon film formed on a semiconductor substrate via an insulating film; forming a dense pattern and a sparse pattern on the mask layer to form a mask; etching the polycrystalline silicon film with the mask by controlling a temperature of the semiconductor substrate placed in an etching chamber at 50 degrees Celsius or higher, supplying an etching gas composed of a hydrogen bromide containing gas and a fluoromethane based gas into the chamber, and generating plasma in the chamber.
    Type: Application
    Filed: June 20, 2011
    Publication date: October 6, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Osamu MIYAGAWA
  • Patent number: 7989331
    Abstract: A method of manufacturing a semiconductor device including forming a mask layer on a polycrystalline silicon film formed on a semiconductor substrate via an insulating film; forming a dense pattern and a sparse pattern on the mask layer to form a mask; etching the polycrystalline silicon film with the mask by controlling a temperature of the semiconductor substrate placed in an etching chamber at 50 degrees Celsius or higher, supplying an etching gas composed of a hydrogen bromide containing gas and a fluoromethane based gas into the chamber, and generating plasma in the chamber.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: August 2, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Osamu Miyagawa
  • Publication number: 20080085593
    Abstract: A method of manufacturing a semiconductor device including forming a mask layer on a polycrystalline silicon film formed on a semiconductor substrate via an insulating film; forming a dense pattern and a sparse pattern on the mask layer to form a mask; etching the polycrystalline silicon film with the mask by controlling a temperature of the semiconductor substrate placed in an etching chamber at 50 degrees Celsius or higher, supplying an etching gas composed of a hydrogen bromide containing gas and a fluoromethane based gas into the chamber, and generating plasma in the chamber.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 10, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Osamu MIYAGAWA
  • Patent number: 7312158
    Abstract: A method of forming a pattern, including forming first and second films, and a resist film on the second film, patterning the resist film to form a first pattern, etching the first pattern to narrow a width of the lines of the first pattern, etching the second film by using the first pattern as a mask to form a second pattern having a configuration of the first pattern transferred thereto, forming a third film above the substrate to cover the second pattern, filling a recessed portion of the third film corresponding to a gap between the lines of the second pattern with a fourth film, and removing a portion of the third film which is located on opposite sides of the fourth film, and a portion of the first film which is located below the third film to form a third pattern.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: December 25, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Miyagawa, Hideki Oguma
  • Publication number: 20060216938
    Abstract: A method of forming a pattern, including forming first and second films, and a resist film on the second film, patterning the resist film to form a first pattern, etching the first pattern to narrow a width of the lines of the first pattern, etching the second film by using the first pattern as a mask to form a second pattern having a configuration of the first pattern transferred thereto, forming a third film above the substrate to cover the second pattern, filling a recessed portion of the third film corresponding to a gap between the lines of the second pattern with a fourth film, and removing a portion of the third film which is located on opposite sides of the fourth film, and a portion of the first film which is located below the third film to form a third pattern.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 28, 2006
    Inventors: Osamu Miyagawa, Hideki Oguma
  • Publication number: 20050215062
    Abstract: A method of manufacturing a semiconductor device involves etching a film of a metal oxide formed above a semiconductor substrate, by using an etching gas. The etching gas includes a reducing gas which is capable of reducing the metal oxide and is non-reactive with the metal, and a reactive gas which is capable of etching the metal.
    Type: Application
    Filed: March 15, 2005
    Publication date: September 29, 2005
    Inventors: Osamu Miyagawa, Masaki Narita, Tokuhisa Ohiwa