Patents by Inventor Osamu Moriyama

Osamu Moriyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230419928
    Abstract: An indicator device includes a plurality of light emitters and at least one processor. The processor obtains, at intervals of a first period, a first period maximum value representing a maximum volume among a plurality of pieces of volume information based on an input signal. The processor obtains, for each second period including a plurality of first periods each being the first period, a minimum value among first period maximum values each being the first period maximum value as a second period minimum value and a maximum value among the first period maximum values as a second period maximum value. The processor controls light emission of the light emitters based on a relative ratio of a predetermined first period maximum value among the first period maximum values. The relative ratio is based on the second period minimum value and the second period maximum value.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 28, 2023
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Tomoya KAJIKAWA, Shingo OKANO, Osamu MORIYAMA, Ken TERAO
  • Publication number: 20230410775
    Abstract: An input interface device includes at least one processor. The processor performs control to cause, among light emitters, a first light emitter corresponding to a contact/proximity point detected by a detector to emit light with a luminous intensity higher than that of a remaining light emitter. The contact/proximity point is where an object is in contact with or in proximity to a detection surface. The processor further performs control, while the object is moving along the light emitters in a state in which the object is in contact with or in proximity to the detection surface, to gradually reduce a luminous intensity of, among the light emitters, a second light emitter corresponding to a point where the object being in contact with or in proximity to the detection surface once detected by the detector is no longer detected to put out the second light emitter in a predetermined time.
    Type: Application
    Filed: May 19, 2023
    Publication date: December 21, 2023
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Tomoya KAJIKAWA, Shingo OKANO, Osamu MORIYAMA, Ken TERAO, Shinichi MORITANI, Yutaro ICHIMURA
  • Publication number: 20230410773
    Abstract: An electronic musical instrument includes an input device that receives an input operation, a display, and a processor. The processor performs a first process upon duration of a detected continuation of the input operation being a reference time or longer. The processor performs a second process upon duration of a detected continuation of the input operation being less than the reference time. The processor causes the display to display a content from which it is determinable whether or not duration of a detected continuation of the input operation being the reference time or longer.
    Type: Application
    Filed: June 13, 2023
    Publication date: December 21, 2023
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Shingo OKANO, Akira IKEDA, Ken TERAO, Shinichi MORITANI, Tomoya KAJIKAWA, Osamu MORIYAMA
  • Publication number: 20230410772
    Abstract: Disclosed is an electronic device including: a display; a detector that detects contact or proximity between an operating body and a detection surface; multiple light emitters that are provided at a position corresponding to the detector, and cause the detection surface to emit light; and at least one processor. The processor performs control to link displaying regarding at least part of a content on the display with light emission of at least part of the light emitters.
    Type: Application
    Filed: May 18, 2023
    Publication date: December 21, 2023
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Tomoya KAJIKAWA, Shingo OKANO, Osamu MORIYAMA, Ken TERAO, Shinichi MORITANI, Yutaro ICHIMURA
  • Publication number: 20230413403
    Abstract: An electronic musical instrument includes an operation receiver that receives an input operation and a processor. The operation receiver includes a rotating wheel. The rotating wheel includes a first light emitter that emits colored light. The processor causes, upon the rotating wheel receiving an input operation, the first light emitter to change an emission color from a color at a start of the input operation to a color corresponding to a rotation angle of the rotating wheel having received the input operation.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 21, 2023
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Shingo OKANO, Akira IKEDA, Ken TERAO, Osamu MORIYAMA, Tomoya KAJIKAWA, Yutaro ICHIMURA
  • Publication number: 20230410779
    Abstract: An electronic device includes: a memory including a data region that stores data; a display device; and at least one processor. At least one processor executes: first boot processing in which a boot time is constant irrespective of a usage state of data in the data region, first output processing of outputting information of a first pattern to the display device during execution of the first boot processing, second boot processing in which a boot time varies depending on a usage state of the data, and second output processing of outputting information of a second pattern to the display device until the second boot processing is completed.
    Type: Application
    Filed: June 12, 2023
    Publication date: December 21, 2023
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Shingo OKANO, Tomoya KAJIKAWA, Osamu MORIYAMA, Shinichi MORITANI, Yutaro ICHIMURA, Akira MIYATA, Ken TERAO
  • Patent number: 10593645
    Abstract: A semiconductor device, includes: a first semiconductor chip including: a first substrate; a first via; a first rear surface-side pad connected to the first via; a first wiring layer; a first front surface-side pad formed on the first wiring layer; and an input circuit formed in the first substrate, an input signal wire connecting the first via, the first front surface-side pad, and an input terminal of the input circuit; and a second semiconductor chip including: a second substrate; a second wiring layer; a second front surface-side pad; and an output circuit formed in the second substrate, an output signal wire connecting the second front surface-side pad to an output terminal of the output circuit. The second semiconductor chip is stacked on a rear surface side of the first semiconductor chip, and the first rear surface-side pad and the second front surface-side pad are connected.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: March 17, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takahiro Shikibu, Yusuke Hamada, Osamu Moriyama
  • Patent number: 10109265
    Abstract: An effect providing apparatus is provided which ostensibly increases the number of effects that can be simultaneously provided. When switching to flanger processing is performed while filter processing in accordance with a periodic signal (LFO signal) is being performed in an effect processing section that can provide only one effect, a CPU advances the periodic signal (LFO signal) from a phase at the time of the switching, and performs the filter processing in accordance with the advancing periodic signal when the flanger processing is ended. As a result of this configuration, the number of effects that can be simultaneously provided is ostensibly increased.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: October 23, 2018
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Osamu Moriyama
  • Patent number: 10008191
    Abstract: A playback device includes a first buffer and a second buffer, each having storage regions, and a processing unit. The processing unit performs: a storage process that causes input audio data to be stored in the storage regions of the first buffer in order; a first playback process that causes the stored audio data to be played back in the order in which the audio data was stored; a designation process that designates, in response to a user input, at least one of the plurality of storage regions of the first buffer in which the audio data is stored; a copy process that causes the audio data stored in the designated storage region of the first buffer to be copied to the second buffer; and a second playback process that causes the audio data copied to the second buffer to be repeatedly played back.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: June 26, 2018
    Assignee: CASIO COMPUTER CO., LTD.
    Inventors: Taiju Suzuki, Osamu Moriyama, Fumiaki Ota
  • Publication number: 20180090113
    Abstract: An effect providing apparatus is provided which ostensibly increases the number of effects that can be simultaneously provided. When switching to flanger processing is performed while filter processing in accordance with a periodic signal (LFO signal) is being performed in an effect processing section that can provide only one effect, a CPU advances the periodic signal (LFO signal) from a phase at the time of the switching, and performs the filter processing in accordance with the advancing periodic signal when the flanger processing is ended. As a result of this configuration, the number of effects that can be simultaneously provided is ostensibly increased.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 29, 2018
    Applicant: CASIO COMPUTER CO., LTD.
    Inventor: Osamu MORIYAMA
  • Patent number: 9835685
    Abstract: A test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device; signal paths provided between one semiconductor chip in the semiconductor chips and another semiconductor chip in the semiconductor chips, data supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating expected values via one or more signal paths in the signal paths, a select signal indicating the one or more signal paths; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: December 5, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Gen Oshiyama, Takahiro Shikibu, Osamu Moriyama, Iwao Yamazaki, Akihiro Chiyonobu
  • Patent number: 9797949
    Abstract: A test circuit, provided to a semiconductor device including a plurality of semiconductor chips, includes: a test clock terminal provided to a first chip; a plurality of clock paths disposed between the first chip and a second chip through which the test clock is transmitted from the first chip to the second chip; a test unit provided to the second chip for testing the second chip by using the test clock transmitted to the second chip; a clock detection unit provided to the second chip, and detects the test clock that is received through each of the plurality of clock paths; and a clock path selection unit which is provided to the second chip, selects a first clock path among the plurality of clock paths as a test clock path, and supplies the test clock transmitted through the test clock path to the test unit.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: October 24, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Gen Oshiyama, Osamu Moriyama, Takahiro Shikibu, Akihiro Chiyonobu, Iwao Yamazaki
  • Patent number: 9746878
    Abstract: A semiconductor device includes chips, wherein a first chip: an internal circuit; first selectors to output signals from one of first outputs; second selectors to output signals from one of second outputs; first output buffer units to relay/interrupt signals output from one of the first outputs; second output buffer units to relay/interrupt signals output from one of the second outputs; first terminals to output a signal from the respective first output buffer units and belong to a first group in which the first terminals are placed at positions distant by first distances; and second terminals to output a signal from the respective second output buffer units and belong to a second group in which the second terminals are placed at positions distant by second distances and each of the second terminals is placed at a position distant from an adjacent first terminal of the first terminals by third distances.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: August 29, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Gen Oshiyama, Takahiro Shikibu, Osamu Moriyama
  • Patent number: 9704463
    Abstract: A musical sound control apparatus includes: an operator which as an index portion and changes values of a plurality of kinds of parameters by moving a position of the index portion; and a parameter control unit which executes processing of changing the values of the plurality of kinds of parameters according to an operated position as a position at which the index portion was moved from a standard position by an operation and processing of, when changing an assignment to the operator from a first parameter among the plurality of kinds of parameters to a second parameter among the plurality of kinds of parameters in a state in which the index portion is positioned at a position other than the standard position, setting a value of the second parameter assigned to a value which does not correspond to the position of the index portion.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: July 11, 2017
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Osamu Moriyama
  • Publication number: 20170033085
    Abstract: A semiconductor device, includes: a first semiconductor chip including: a first substrate; a first via; a first rear surface-side pad connected to the first via; a first wiring layer; a first front surface-side pad formed on the first wiring layer; and an input circuit formed in the first substrate, an input signal wire connecting the first via, the first front surface-side pad, and an input terminal of the input circuit; and a second semiconductor chip including: a second substrate; a second wiring layer; a second front surface-side pad; and an output circuit formed in the second substrate, an output signal wire connecting the second front surface-side pad to an output terminal of the output circuit. The second semiconductor chip is stacked on a rear surface side of the first semiconductor chip, and the first rear surface-side pad and the second front surface-side pad are connected.
    Type: Application
    Filed: July 22, 2016
    Publication date: February 2, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Takahiro Shikibu, Yusuke Hamada, Osamu Moriyama
  • Patent number: 9443499
    Abstract: A musical sound control apparatus (1) includes a slider (17a), a CPU (11) and a recording ring buffer (13a). The slider (17a) enables scratching in both directions. The CPU (11) plays back musical sound data being sequentially supplied. The recording ring buffer (13a) rapidly stores, in response to emit a sound of the musical sound data being supplied, the musical sound data. The CPU (11), in a case of a scratch operation being performed on the slider (17a), controls so as to read out and playback the musical sound data stored in the recording ring buffer (13a) in place of the musical sound data being supplied, based on a direction and operation speed of the scratch operation.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 13, 2016
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Osamu Moriyama
  • Publication number: 20160187421
    Abstract: A test circuit, provided to a semiconductor device including a plurality of semiconductor chips, includes: a test clock terminal provided to a first chip; a plurality of clock paths disposed between the first chip and a second chip through which the test clock is transmitted from the first chip to the second chip; a test unit provided to the second chip for testing the second chip by using the test clock transmitted to the second chip; a clock detection unit provided to the second chip, and detects the test clock that is received through each of the plurality of clock paths; and a clock path selection unit which is provided to the second chip, selects a first clock path among the plurality of clock paths as a test clock path, and supplies the test clock transmitted through the test clock path to the test unit.
    Type: Application
    Filed: October 21, 2015
    Publication date: June 30, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Gen OSHIYAMA, Osamu Moriyama, Takahiro Shikibu, Akihiro Chiyonobu, Iwao Yamazaki
  • Publication number: 20160154049
    Abstract: A semiconductor device includes chips, wherein a first chip: an internal circuit; first selectors to output signals from one of first outputs; second selectors to output signals from one of second outputs; first output buffer units to relay/interrupt signals output from one of the first outputs; second output buffer units to relay/interrupt signals output from one of the second outputs; first terminals to output a signal from the respective first output buffer units and belong to a first group in which the first terminals are placed at positions distant by first distances; and second terminals to output a signal from the respective second output buffer units and belong to a second group in which the second terminals are placed at positions distant by second distances and each of the second terminals is placed at a position distant from an adjacent first terminal of the first terminals by third distances.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 2, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Gen OSHIYAMA, Takahiro Shikibu, Osamu Moriyama
  • Publication number: 20160154057
    Abstract: A test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device; signal paths provided between one semiconductor chip in the semiconductor chips and another semiconductor chip in the semiconductor chips, data supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating expected values via one or more signal paths in the signal paths, a select signal indicating the one or more signal paths; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 2, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Gen OSHIYAMA, Takahiro Shikibu, Osamu Moriyama, Iwao Yamazaki, Akihiro Chiyonobu
  • Publication number: 20160086589
    Abstract: A musical sound control apparatus (1) includes a slider (17a), a CPU (11) and a recording ring buffer (13a). The slider (17a) enables scratching in both directions. The CPU (11) plays back musical sound data being sequentially supplied. The recording ring buffer (13a) rapidly stores, in response to emit a sound of the musical sound data being supplied, the musical sound data. The CPU (11), in a case of a scratch operation being performed on the slider (17a), controls so as to read out and playback the musical sound data stored in the recording ring buffer (13a) in place of the musical sound data being supplied, based on a direction and operation speed of the scratch operation.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 24, 2016
    Applicant: CASIO COMPUTER CO., LTD.
    Inventor: Osamu MORIYAMA