Abstract: An image sensor device includes a plurality of pixel cells arranged in a matrix in a pixel array, and a timing control circuit that controls read-out of pixel information from the plurality of pixel cells. Each of the plurality of pixel cells includes a photodiode, a transfer transistor provided between the photodiode and a floating diffusion, a node reset transistor provided between a power supply terminal and the floating diffusion, a read-out capacitor whose one end is connected to the power supply terminal, a capacitor reset transistor provided between another end of the read-out capacitor and the floating diffusion, an amplification transistor that amplifies a voltage generated based on electric charges accumulated in the floating diffusion, and a selection transistor provided between the amplification transistor and a read-out line.

Abstract: The present disclosure is provided to solve a problem that a signal obtained by imaging with low illumination cannot be amplified while suppressing random noise. An AD converter outputs n bits. A digital converting unit converts each of P pieces of analog signals output from the same place at different times to a digital value of (n?m) bits. An addition circuit integrates P pieces of the converted digital values. Here, n denotes a natural number of 1 or larger, m denotes a natural number of 1 or larger and less than n, and P denotes a natural number of 1 or larger and m or less.

Abstract: An image sensor device includes a plurality of pixel cells arranged in a matrix in a pixel array, and a timing control circuit that controls read-out of pixel information from the plurality of pixel cells. Each of the plurality of pixel cells includes a photodiode, a transfer transistor provided between the photodiode and a floating diffusion, a node reset transistor provided between a power supply terminal and the floating diffusion, a read-out capacitor whose one end is connected to the power supply terminal, a capacitor reset transistor provided between another end of the read-out capacitor and the floating diffusion, an amplification transistor that amplifies a voltage generated based on electric charges accumulated in the floating diffusion, and a selection transistor provided between the amplification transistor and a read-out line.

Abstract: Image sensor devices of related art have a problem that a circuit area increases. According to one embodiment, an image sensor device includes a read-out capacitor (28) that accumulates first pixel information to be output from a photodiode which is exposed to light with a first exposure time. In addition to the first pixel information, second pixel information to be output from the photodiode which is exposed to light with a second exposure time longer than the first exposure time is generated. After the first pixel information and the second pixel information are read out separately, the two pieces of pixel information are synthesized to thereby generate output image information.

Abstract: As a reset transistor is turned on, an FD (Floating Diffusion) is reset to VDD and then stores charges transferred from a light receiving element. By a source-follower circuit formed by an amplifying transistor, a selection transistor and a current source, a voltage in accordance with a potential of FD is output to a data line. A second output circuit generates an output voltage VOUT in accordance with the potential of FD at an output node. Output transistors in output circuit are configured to generate a potential difference equivalent to the potential difference between FD and data line caused by the amplifying transistor and selection transistor, between data line and output node.

Abstract: There is a need to provide an AD converter capable of reducing occurrence of a noise. An AD converter includes an operational amplifier and a clip circuit. The operational amplifier receives ramp voltage and voltage for an analog signal and allows output terminal voltage to transition from an H level to an L level when a change in the ramp voltage reaches the voltage for the analog signal. The clip circuit fixes an output terminal of the operational amplifier to clipping voltage after output voltage for the operational amplifier reaches threshold voltage for a latch circuit. Therefore, the AD converter can limit a range of output voltage, as a source of noise, for the operational amplifier and eliminate an unnecessary change in the output voltage after the threshold voltage for the latch circuit is reached.

Abstract: There is a need to provide an AD converter capable of reducing occurrence of a noise. An AD converter includes an operational amplifier and a clip circuit. The operational amplifier receives ramp voltage and voltage for an analog signal and allows output terminal voltage to transition from an H level to an L level when a change in the ramp voltage reaches the voltage for the analog signal. The clip circuit fixes an output terminal of the operational amplifier to clipping voltage after output voltage for the operational amplifier reaches threshold voltage for a latch circuit. Therefore, the AD converter can limit a range of output voltage, as a source of noise, for the operational amplifier and eliminate an unnecessary change in the output voltage after the threshold voltage for the latch circuit is reached.

Abstract: As a reset transistor is turned on, an FD (Floating Diffusion) is reset to VDD and then stores charges transferred from a light receiving element. By a source-follower circuit formed by an amplifying transistor, a selection transistor and a current source, a voltage in accordance with a potential of FD is output to a data line. A second output circuit generates an output voltage VOUT in accordance with the potential of FD at an output node. Output transistors in output circuit are configured to generate a potential difference equivalent to the potential difference between FD and data line caused by the amplifying transistor and selection transistor, between data line and output node.

Abstract: There is a need to provide an AD converter capable of reducing occurrence of a noise. An AD converter includes an operational amplifier and a clip circuit. The operational amplifier receives ramp voltage and voltage for an analog signal and allows output terminal voltage to transition from an H level to an L level when a change in the ramp voltage reaches the voltage for the analog signal. The clip circuit fixes an output terminal of the operational amplifier to clipping voltage after output voltage for the operational amplifier reaches threshold voltage for a latch circuit. Therefore, the AD converter can limit a range of output voltage, as a source of noise, for the operational amplifier and eliminate an unnecessary change in the output voltage after the threshold voltage for the latch circuit is reached.

Abstract: An AM demodulator includes an APC detection circuit that compares phases of an AM-modulated input signal and a signal output from a VCO. However, the APC detection circuit multiples the two signals before their comparison. As a result, even if the phases of the input signal or the signal output from the VCO is shifted by 180 degrees, the result of comparison by the APC detection circuit is not influenced by the phase shift. Moreover, when a signal detected by the AM detection circuit is in a potential range showing over-modulation, operation of a PLL circuit is stopped.

Abstract: An AM detecting apparatus includes a voltage comparator And an AND circuit. The voltage comparator compares a detection signal a low-pass filter outputs with a no-signal potential. The AND circuit outputs, when the amplitude of an AM signal is higher than the reference value, one of a first control signal and second control signal in response to a comparison result of the voltage comparator 5, and outputs, when the amplitude of the AM signal is lower than the reference value, the first control signal. The phase of the VCO signal is controlled such that the phase difference between the AM signal and VCO signal agrees with the control signal the AND circuit outputs. The AM detecting apparatus can carry out the coherent detection of the desired signal in the AM signal even during overmodulation.

Abstract: A first automatic phase control (APC) detection circuit generates an APC detection signal having normal polarity from an amplitude modulation signal and APC detection reference signal. A second APC detection circuit generates an APC detection signal having reverse polarity from the amplitude modulation signal and the APC detection reference signal. A switch selects the APC detection signal having normal polarity in case of normal modulation and selects the APC detection signal having reverse polarity in case of overmodulation.

Abstract: An AM detecting apparatus includes a voltage comparator And an AND circuit. The voltage comparator compares a detection signal a low-pass filter outputs with a no-signal potential. The AND circuit outputs, when the amplitude of an AM signal is higher than the reference value, one of a first control signal and second control signal in response to a comparison result of the voltage comparator 5, and outputs, when the amplitude of the AM signal is lower than the reference value, the first control signal. The phase of the VCO signal is controlled such that the phase difference between the AM signal and VCO signal agrees with the control signal the AND circuit outputs. The AM detecting apparatus can carry out the coherent detection of the desired signal in the AM signal even during overmodulation.

Abstract: The AM demodulator includes the APC detection circuit that compares phases of the AM-modulated input signal and the signal output from VCO. However, the APC detection circuit multiples the two signals before their comparison. As a result, even if the phases of the input signal or the signal output from VCO is shifted by 180 degrees, the result of comparison by the APC detection circuit is not influenced due to the phase shift. Moreover, in the case where a signal detected by the AM detection circuit is in a predetermined potential range showing over-modulation, an operation of a PLL circuit is rest.

Abstract: In an automatic gain control (AGC) circuit based on a peak detection system having two filters, a voltage comparator selects one of two voltages and compares the selected voltage with a detection signal output from a wave detector. A second AGC filter selects a cut-off frequency based on the result of comparison of the voltage comparator and supplies a signal resulting from low-pass filtering, based on the selected cut-off frequency, to a voltage-controlled amplifier as a control voltage. When a highly modulated signal is abruptly input, selection of the cut-off frequency of the second AGC filter occurs.