Abstract: A method of manufacturing a wiring harness includes the processes of 1) making plural kinds of electric wires each having a predetermined length (w1, w2, w3, . . . ) for each kind in lots (L1, L2, L3, . . . ) each having several tens to several hundreds wires, the plural kinds of wires constituting a wiring harness and including terminal-equipped wires with one end or both ends connected with a terminal(s) and terminal-free wires with both ends connected to no terminal; 2) temporarily holding groups of wires thus made (L1, L2, L3, . . . ) in predetermined wire holders (H1, H2, H3, . . . ) in the order of lots; and 3) wire arrangement of forming a set of wires for the wiring harness with the groups of wires constituting the wiring harness intensively hung on one or more wire clamps in such a manner that one wire w1 is taken out from the wire holder H1 to lock its one or both ends to predetermined one or two wire clips of the wire clamp provided with plural wire clips, and subsequently, the wires (w2, w3, . . .

Abstract: A method of manufacturing a wiring harness including the steps of making plural kinds of electric wires each having a predetermined length for each kind in lots each having several tens to several hundreds wires, the plural kinds of wires constituting a wiring harness and including terminal-equipped wires with one or both ends connected with a terminal and terminal-free wires with both ends connected to no terminal; temporarily holding groups of wires thus made in predetermined wire holders in the order of lots; and wire arrangement accomplished by forming a set of wires for the wiring harness with the groups of wires constituting the wiring harness intensively hung on one or more wire clamps in such a manner that one wire w1 is taken out from the wire holder H1 to lock its one or both ends to predetermined one or two wire clips of the wire clamp provided with plural wire clips, and subsequently, the wires (w2, w3, . . .) are taken out in order one-by-one from each of the wire holders (H2, H3, . . .

Abstract: A CMOS master slice having a plurality of regularly arranged basic cells improves an integration efficiency by optimizing size and arrangement of MOS transistors in the basic cells. Each of the basic cells comprises a first pair of transistors having gates thereof arranged to parallelly face each other, and a second pair of transistors having gate electrodes shorter in gate width than that of the first pair of transistors and parallel to the gate electrodes of the first pair of transistors. In adjacent basic cells, the gate electrodes of adjacent second transistors are substantially on a line so that a wasteful space is eliminated.