Abstract: An encoder includes a semiconductor laser capable of emitting two coherent light beams from two end faces thereof, respectively. The end faces of the semiconductor laser are arranged such that the coherent light beams intersect each other. The two coherent light beams emitted from the end faces of the semiconductor laser are incident on a scale having a plurality of gratings. The two coherent light beams are diffracted by the gratings, resulting in two diffracted light beams. The two diffracted light beams interfere with each other, and the intensity of the resultant interference light beam is detected by a detector. In response to this detection, the detector produces a signal corresponding to the intensity change which is proportional to the relative moving distance between the detector and the scale.

Abstract: An address pattern generator for use in a test pattern generator for generating various patterns for testing semiconductor memories. A plurality of fixed registers for storing an initial value at the start of a test, a boundary value and an operand indicating the amount of change of an address are provided in common to at least two address operating circuits. The address operating circuits are each capable of taking therein the content of a desired one of the fixed registers. At least two output registers are provided, which are each capable of taking therein the operation result of a desired one of the address operating circuit. The contents of these output registers are supplied as addresses to a memory under test.

Abstract: A test pattern generating apparatus in which a microprogram describing a test pattern to be generated is read for interpretation and execution, address and data patterns are generated by arithmetic operations and a memory control signal is produced, the address and data patterns and the memory control signal being applied to a memory under test. The address pattern is provided to an area inversion control signal generation section to produce an inversion control signal corresponding to the address pattern, by which the data pattern may be inverted and then outputted.