Patents by Inventor Osamu Okano

Osamu Okano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Test pattern generator, test circuit tester, test pattern generating method, test circuit testing method, and computer product
    Patent number: 7516376
    Abstract: A test circuit tester includes a scan-chain input-output information generator that generates information for an input and an output of the scan chain that is scan-chain input-output information, based on input information for the scan chain; a test-circuit input-output information generator that generates information for an input and an output of the test circuit that is test-circuit input-output information, based on the scan-chain input-output information; an output unit that outputs the test-circuit input-output information generated; and a verifying unit that verifies the test circuit based on an output pattern output from the test circuit through the scan chains in response to input of the information for the input of the test circuit output to the test circuit, and the information for the output from the test circuit.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: April 7, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Osamu Okano, Hideaki Konishi
  • Test pattern generator, test circuit tester, test pattern generating method, test circuit testing method, and computer product
    Publication number: 20050289419
    Abstract: A test circuit tester includes a scan-chain input-output information generator that generates information for an input and an output of the scan chain that is scan-chain input-output information, based on input information for the scan chain; a test-circuit input-output information generator that generates information for an input and an output of the test circuit that is test-circuit input-output information, based on the scan-chain input-output information; an output unit that outputs the test-circuit input-output information generated; and a verifying unit that verifies the test circuit based on an output pattern output from the test circuit through the scan chains in response to input of the information for the input of the test circuit output to the test circuit, and the information for the output from the test circuit.
    Type: Application
    Filed: October 20, 2004
    Publication date: December 29, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Osamu Okano, Hideaki Konishi
  • Method and apparatus for supporting designing of LSI, and computer product
    Publication number: 20050172254
    Abstract: A design support apparatus includes a unit that inputs a user net list created by using hard macro cells excluding test circuits, and a unit that arranges hard macro cells using a frame into which hard macro cells, where timing-converged physical information includes test terminals, and test circuits are embedded as arrangement/wiring information. Moreover, includes a unit that arranges and wires the test circuits using the arrangement/wiring information of the test circuit embedded into the frame, a unit that recognizes arrangement/wiring information where the arrangement/wiring information of the test circuits is removed from arrangement/wiring information obtained by wiring, and a unit outputs a net list of a logic structure.
    Type: Application
    Filed: May 17, 2004
    Publication date: August 4, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Hitoshi Watanabe, Hideaki Konishi, Yuko Katoh, Kazuyuki Yamamura, Naoko Karasawa, Takeshi Doi, Osamu Okano, Junko Kumagai, Koichi Itaya, Daisuke Tsukuda, Ryuji Shimizu, Toshihito Shimizu